Patents by Inventor Tsu Chieh Ai

Tsu Chieh Ai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240049448
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventor: TSU-CHIEH AI
  • Publication number: 20240040771
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Inventor: TSU-CHIEH AI
  • Patent number: 11877436
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsu-Chieh Ai
  • Patent number: 11832439
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsu-Chieh Ai
  • Patent number: 11823992
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: November 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsu-Chieh Ai
  • Publication number: 20230231006
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.
    Type: Application
    Filed: March 22, 2023
    Publication date: July 20, 2023
    Inventor: TSU-CHIEH AI
  • Publication number: 20230187481
    Abstract: A method for forming a capacitor array includes depositing a first nitride layer, a first oxide layer, and a second nitride layer in sequence over first and second contacts on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form first and second openings exposing the first and second contacts; conformally depositing a bottom electrode layer over the first and second nitride layers and the first oxide layer and on the first and second contacts; etching the second nitride layer and the first oxide layer to form a third opening having a bottom position higher than a top surface of the first nitride layer; removing the first oxide layer through the third opening; forming a capacitor dielectric layer over the bottom electrode layer; forming a top electrode layer over the capacitor dielectric layer.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventor: Tsu Chieh AI
  • Publication number: 20230109118
    Abstract: An interconnection structure and a method of manufacturing an interconnection structure are provided. The interconnection structure includes a first dielectric layer, a first conductive via in the first dielectric layer, and a first metal line disposed on the first dielectric layer and electrically connected with the first conductive via. At least a portion of the first metal line is exposed to a first air gap.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Inventor: TSU-CHIEH AI
  • Publication number: 20230105066
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.
    Type: Application
    Filed: September 24, 2021
    Publication date: April 6, 2023
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: TSU-CHIEH AI
  • Publication number: 20230094890
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially-disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventor: Tsu-Chieh AI
  • Publication number: 20230099828
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: TSU-CHIEH AI
  • Patent number: 11605704
    Abstract: A capacitor array includes a substrate, first pedestal container stacked capacitors, second pedestal container stacked capacitors, and third pedestal container stacked capacitors. The first pedestal container stacked capacitors extend upwardly from above the substrate and are arranged in a first row. The second pedestal container stacked capacitors extend upwardly from above the substrate and are arranged in a second row next to the first row. The third pedestal container stacked capacitors extend upwardly from above the substrate and are arranged in a third row next to the second row. A first distance between the first and second rows is less than a second distance between the second and third rows.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: March 14, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsu Chieh Ai