Patents by Inventor Tsu-Hui YANG

Tsu-Hui YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069452
    Abstract: Embodiments of the present disclosure relate to projection stabilization systems and maskless lithography systems having projection stabilization systems. The projection stabilization system compensates for propagating vibrations that move image projection systems (IRS's). The IRS's are in a processing positon prior to operation of the maskless lithography process. One or more stiffeners are coupled to the IPS. The one or more stiffeners apply pressure to flexures coupled to each stiffener. The flexures are coupled to the IPS to provide stabilization to the IPS during the operations of the maskless lithography process. For example, the one or more of stiffeners protect the IPS from vibrations that propagate through the system during operation.
    Type: Application
    Filed: February 1, 2022
    Publication date: February 29, 2024
    Inventors: Assaf KIDRON, Jiawei SHI, Liang-Yuh CHEN, Che-Kai CHANG, Tsu-Hui YANG, Nimrod SMITH, Grant WANG, Preston FUNG, Vasuman Ghanapaati SRIRANGARAJAN, Davidi KALIR, Rudolf C. BRUNNER
  • Patent number: 10928743
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Chia-Hung Kao, Hsiu-Jen Wang, Shih-Hao Kuo, Yi-Sheng Liu, Shih-Hsien Lee, Ching-Chang Chen, Tsu-Hui Yang
  • Publication number: 20190369499
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Application
    Filed: March 19, 2019
    Publication date: December 5, 2019
    Inventors: Chien-Hua LAI, Chia-Hung KAO, Hsiu-Jen WANG, Shih-Hao KUO, Yi-Sheng LIU, Shih-Hsien LEE, Ching-Chang CHEN, Tsu-Hui YANG
  • Patent number: 10459341
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Publication number: 20190235389
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Application
    Filed: December 11, 2018
    Publication date: August 1, 2019
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Publication number: 20140097728
    Abstract: A vibration suppression casing is suitable for a computing system including a chassis, a mainboard, and an electronic device. The mainboard is disposed in the chassis. The electronic device is disposed in the chassis. The computing system is adapted to generate a vibration wave while running The vibration suppression casing includes a case body and a vibration suppression unit. The case body is detachably attached to the chassis. The vibration suppression unit, disposed on the case body, includes a base, an elastic arm and a balancing weight. The base is securely disposed on the case body. The elastic arm has a first end and a second end opposite to each other. The first end is connected to the base. The balancing weight is disposed on the second end. The balancing weight moves in conjunction with the movement of the attached base, driven by the vibration wave.
    Type: Application
    Filed: March 18, 2013
    Publication date: April 10, 2014
    Applicants: INVENTEC CORPORATION, INVENTEC (PUDONG) TECHNOLOGY CORPORATION
    Inventor: Tsu-Hui YANG