Patents by Inventor Tsu-Jae King Liu
Tsu-Jae King Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7807523Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. A multi step epitaxial process can be used to extend the ridges with different dopant types, high mobility semiconductor, and or advanced multi-layer strutures.Type: GrantFiled: January 30, 2007Date of Patent: October 5, 2010Assignee: SYNOPSYS, Inc.Inventors: Tsu Jae King Liu, Qiang Lu
-
Publication number: 20100184276Abstract: A method for forming polycrystalline semiconductor film from amorphous semiconductor film at reduced temperatures and/or accelerated rates. The inclusion of a small percentage of semiconductor material, such as 2% within the metal layer, reduces the temperatures required for crystallization of the amorphous semiconductor by at least 50° C. in comparison to the use of the metal layer without the small percentage of semiconductor material. During a low temperature isothermal annealing process adjacent Al-2% Si and a-Si films undergo a layer exchange resulting in formation of a continuous polycrystalline silicon film having good physical and electrical properties. Formation of polycrystalline-semiconductor in this manner is suitable for use with low temperature substrates (e.g., glass, plastic) as well as with numerous integrated circuit and MEMs fabrication devices and practices.Type: ApplicationFiled: December 31, 2009Publication date: July 22, 2010Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Roya Maboudian, Frank W. Delrio, Joanna Lai, Tsu-Jae King Liu
-
Patent number: 7710771Abstract: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.Type: GrantFiled: August 7, 2007Date of Patent: May 4, 2010Assignee: The Regents of the University of CaliforniaInventors: Charles C. Kuo, Tsu-Jae King Liu
-
Patent number: 7605449Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g.Type: GrantFiled: January 30, 2007Date of Patent: October 20, 2009Assignee: Synopsys, Inc.Inventors: Tsu Jae King Liu, Qiang Lu
-
Patent number: 7560201Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.Type: GrantFiled: July 23, 2008Date of Patent: July 14, 2009Assignee: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Patent number: 7537866Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.Type: GrantFiled: May 24, 2006Date of Patent: May 26, 2009Assignee: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Publication number: 20090114953Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.Type: ApplicationFiled: January 12, 2009Publication date: May 7, 2009Applicant: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Patent number: 7508031Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably produced. Ridges on the corrugated substrate can be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy.Type: GrantFiled: January 30, 2007Date of Patent: March 24, 2009Assignee: Synopsys, Inc.Inventors: Tsu Jae King Liu, Qiang Lu
-
Patent number: 7494933Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.Type: GrantFiled: June 16, 2006Date of Patent: February 24, 2009Assignee: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Publication number: 20090039438Abstract: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.Type: ApplicationFiled: October 13, 2008Publication date: February 12, 2009Applicant: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Publication number: 20090010056Abstract: A method and/or system and/or apparatus for a dual gate, capacitor less circuit that can act as a state storage device. Further embodiments describe fabrication methods and methods of operation of such a device.Type: ApplicationFiled: August 7, 2007Publication date: January 8, 2009Inventors: Charles C. Kuo, Tsu-Jae King Liu
-
Publication number: 20080296632Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicant: Synopsys, Inc.Inventors: Victor Moroz, Tsu-Jae King Liu
-
Publication number: 20080280217Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.Type: ApplicationFiled: July 23, 2008Publication date: November 13, 2008Applicant: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Publication number: 20080057712Abstract: A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.Type: ApplicationFiled: June 16, 2006Publication date: March 6, 2008Applicant: Synopsys, Inc.Inventor: Tsu-Jae King Liu
-
Publication number: 20070275309Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.Type: ApplicationFiled: May 24, 2006Publication date: November 29, 2007Applicant: Synopsys, Inc.Inventor: Tsu-Jae King Liu