Patents by Inventor Tsu Lee

Tsu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015246
    Abstract: A semiconductor device is provided, which includes an active region, a first semiconductor layer, a first metal element-containing structure, a first p-type or n-type layer, a second semiconductor layer and an insulating layer. The active region has a first surface and a second surface. The first semiconductor layer is at the first surface. The first metal element-containing structure covers the first semiconductor layer and comprising a first metal element. The first p-type or n-type layer is between the first semiconductor layer and the first metal element-containing structure. The second semiconductor layer is between the first semiconductor layer and the first p-type or n-type layer. The insulating layer covers a portion of the first semiconductor layer and a portion of the second semiconductor. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Inventors: Yu-Tsu LEE, Yi-Yang CHIU, Chun-Wei CHANG, Min-Hao YANG, Wei-Jen HSUEH, Yi-Ming CHEN, Shih-Chang LEE, Chung-Hao WANG
  • Patent number: 12125956
    Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 22, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yu-Tsu Lee, Yi-Yang Chiu, Chun-Wei Chang, Min-Hao Yang, Wei-Jen Hsueh, Yi-Ming Chen, Shih-Chang Lee, Chung-Hao Wang
  • Publication number: 20240209196
    Abstract: A method of forming an antistatic plastic includes providing a mixture containing 10 parts by weight of crystalline silicon particles, 1 to 30 parts by weight of an encapsulant, and 0.5 to 25 parts by weight of a backsheet material. The mixture is compounded to form an antistatic plastic, wherein the encapsulant is different from the backsheet material.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 27, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chin-Shang HSU, Pang-Hung LIU, Nien-Tsu LEE, Chien-Wei LU
  • Patent number: 12012506
    Abstract: A method of forming an antistatic plastic includes providing a mixture containing 10 parts by weight of crystalline silicon particles, 1 to 30 parts by weight of an encapsulant, and 0.5 to 25 parts by weight of a backsheet material. The mixture is compounded to form an antistatic plastic, wherein the encapsulant is different from the backsheet material.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: June 18, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chin-Shang Hsu, Pang-Hung Liu, Nien-Tsu Lee, Chien-Wei Lu
  • Publication number: 20240194790
    Abstract: The present disclosure provides a semiconductor device including a drift layer above the substrate, a source/drain region above the drift layer, an oxide thin film on the source/drain region, a contact on the oxide thin film, and a gate structure adjacent to source/drain region. The oxide thin film directly contacts the top surface of the source/drain region and the bottom surface of the contact. The source/drain region includes a first doping region having a first conductive type and a second doping region having a second conductive type different from the first conductive type, in which the first doping region and the second doping region forms the top surface of the source/drain region. The conduction band energy level of the oxide thin film is lower than the conduction band energy level of the first doping region.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 13, 2024
    Inventors: Yu-Tsu LEE, Yan-Ru CHEN, Kuang-Hao CHIANG
  • Publication number: 20240186449
    Abstract: The present disclosure provides a semiconductor device including a semiconductor structure, a first metal element-containing structure, and a layer. The semiconductor structure includes a first semiconductor layer having a first material, a second semiconductor layer, an active region between the first semiconductor layer and the second semiconductor layer. The first metal element-containing structure is located on the semiconductor structure and includes a first metal element. The layer has a second material and a second metal element and is located between the first semiconductor layer and the first metal element-containing structure. The first material has a conduction band edge Ec and a valence band edge Ev, and the second material has a work function WF1, when the first semiconductor layer is of an n-type conductivity, the work function WF1 fulfills WF1<(Ec+Ev)/2, and when the first semiconductor layer is of a p-type conductivity, the work function WF1 fulfills WF1>(Ec+Ev)/2.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 6, 2024
    Inventors: Min-Hsun HSIEH, Yu-Tsu LEE, Wei-Jen HSUEH
  • Publication number: 20240120411
    Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.
    Type: Application
    Filed: February 17, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Tsu LEE, Yan-Ru CHEN, Liang-Ming LIU, Kuang-Hao CHIANG
  • Publication number: 20240120410
    Abstract: A semiconductor structure includes a semiconductor epitaxial layer, a first semiconductor well, a second semiconductor well, a source doped region, a gate structure and a drain structure. The semiconductor epitaxial layer includes a first side and a second side opposite to the first side. The first semiconductor well is located on the first side of the semiconductor epitaxial layer. The second semiconductor well is located on the second side of the semiconductor epitaxial layer. The source doped region is located in the first semiconductor well. The gate structure overlaps the first semiconductor well and the source doped region on the first side of the semiconductor epitaxial layer. The drain structure includes a semiconductor substrate. The second side of the semiconductor epitaxial layer outside the second semiconductor well includes a connecting surface. The connecting surface of the semiconductor epitaxial layer is connected to the semiconductor substrate.
    Type: Application
    Filed: February 16, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Tsu LEE, Yan-Ru CHEN, Chao-Yi CHANG, Kuang-Hao CHIANG
  • Patent number: 11894489
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor layer, an active region, a p-type or n-type layer, and a first metal element-containing structure. The first semiconductor layer has a surface including a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP or AlGaInP. The p-type or n-type layer includes an oxygen element (O) and a metal element, and is located on the second portion. The first metal element-containing structure is located on the p-type or n-type layer. The p-type or n-type layer physically contacts the first metal element-containing structure and the first semiconductor layer.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: February 6, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Yu-Tsu Lee, Wei-Jen Hsueh
  • Publication number: 20220302346
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a first semiconductor layer, an active region, a p-type or n-type layer, and a first metal element-containing structure. The first semiconductor layer has a surface including a first portion and a second portion. The active region is located on the first portion and includes AlGaInAs, InGaAsP, AlGaAsP or AlGaInP. The p-type or n-type layer includes an oxygen element (O) and a metal element, and is located on the second portion. The first metal element-containing structure is located on the p-type or n-type layer. The p-type or n-type layer physically contacts the first metal element-containing structure and the first semiconductor layer.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Min-Hsun HSIEH, Yu-Tsu LEE, Wei-Jen HSUEH
  • Publication number: 20220302360
    Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Yu-Tsu LEE, Yi-Yang CHIU, Chun-Wei CHANG, Min-Hao YANG, Wei-Jen HSUEH, Yi-Ming CHEN, Shih-Chang LEE, Chung-Hao WANG
  • Patent number: 10843182
    Abstract: Provided is a composite material including a plurality of porous silicate particles having a glass phase structure, a first active metal adsorbed into the glass phase structure of the porous silicate particles, and a modified layer containing a second active metal formed on the surfaces of the porous silicate particles. The porous silicate particles have an average pore diameter of from 3 nm to 50 nm, and the first active metal includes at least one of sodium, potassium, calcium, and magnesium.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: November 24, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Nien-Tsu Lee, Huan-Yi Hung, Chien-Wei Lu, Hsien-Hui Tai
  • Publication number: 20190151837
    Abstract: Provided is a composite material including a plurality of porous silicate particles having a glass phase structure, a first active metal adsorbed into the glass phase structure of the porous silicate particles, and a modified layer containing a second active metal formed on the surfaces of the porous silicate particles. The porous silicate particles have an average pore diameter of from 3 nm to 50 nm, and the first active metal includes at least one of sodium, potassium, calcium, and magnesium.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Inventors: Nien-Tsu Lee, Huan-Yi Hung, Chien-Wei Lu, Hsien-Hui Tai
  • Patent number: 8875373
    Abstract: A manufacturing method of heat conductive device for an LED has steps of forming a heat sink and an engagement recess in the heat sink by cold forge, punching a heat-conducting disc to form an LED carrier having a mounting portion and a heat-conducting wall formed around the mounting portion, soldering multiple LEDs on the LED carrier, and heating the heat sink to thermally expand the heat sink and assembling the LED carrier and the heat sink so that the heat-conducting wall is assembled with the engagement recess and further chilling the heat sink to thermally retract and tightly hold the LED carrier. The manufacturing method increases contact area and reduces air gaps between the LED carrier and the heat sink to effectively enhance the heat-conducting efficiency of the LED carrier so that the LEDs are operated at a suitable operating temperature to secure a prolonged life duration.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 4, 2014
    Assignee: Pan-Jit International Inc.
    Inventor: Tsu Lee
  • Publication number: 20130070465
    Abstract: A heat conductive device for an LED has a heat sink and an LED carrier tightly fitted in the heat sink. The LED carrier has a mounting portion formed on one end thereof and having a first heat-conducting surface formed on a top of the mounting portion, and a heat-conducting portion formed along a perimeter of the mounting portion and having a second heat-conducting surface formed on the periphery of the heat-conducting portion. The first and second heat-conducting surfaces contact the engagement portion of the heat sink so that heat generated by LED operation is conducted to the heat sink through the heat-conducting portion, the first heat-conducting surface and the second heat-conducting surface. With the second heat-conducting surface of the LED carrier, heat can be more efficiently conducted to the heat sink and LEDs can be operated at an adequate operating temperature to prolong their life duration.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 21, 2013
    Inventor: Tsu LEE
  • Publication number: 20120311849
    Abstract: A manufacturing method of heat conductive device for an LED has steps of forming a heat sink and an engagement recess in the heat sink by cold forge, punching a heat-conducting disc to form an LED carrier having a mounting portion and a heat-conducting wall formed around the mounting portion, soldering multiple LEDs on the LED carrier, and heating the heat sink to thermally expand the heat sink and assembling the LED carrier and the heat sink so that the heat-conducting wall is assembled with the engagement recess and further chilling the heat sink to thermally retract and tightly hold the LED carrier. The manufacturing method increases contact area and reduces air gaps between the LED carrier and the heat sink to effectively enhance the heat-conducting efficiency of the LED carrier so that the LEDs are operated at a suitable operating temperature to secure a prolonged life duration.
    Type: Application
    Filed: September 16, 2011
    Publication date: December 13, 2012
    Applicant: PAN-JIT INTERNATIONAL INC.
    Inventor: Tsu Lee
  • Patent number: 7841752
    Abstract: An LED lighting device having heat convection and heat conduction effects has a heat dissipating assembly, a substrate, multiple LEDs and a base. The heat dissipating assembly has a housing and an outer cover. The housing has multiple air holes. The outer cover is mounted on an open top of the housing and has multiple through holes and an exterior flue protruding from the outer cover and extending into the housing. The substrate is mounted inside the housing against the outer cover and has a hole allowing the exterior flue to extend therethrough. The LEDs are mounted on the substrate and respectively correspond to the through holes. The base is attached to a bottom of the housing. The exterior flue encourages heated air to move through the exterior flue and flow out of the housing via the air holes. With such continuous and directional air movement, the LED lighting device obtains good heat-dissipating efficiency.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 30, 2010
    Assignee: Pan-Jit International Inc.
    Inventor: Tsu Lee
  • Patent number: 7810951
    Abstract: An LED module comprises a heat dissipating bracket, a substrate, multiple LED assemblies and two rotatable mounting assemblies. The heat dissipating bracket has a top panel, a bottom panel and multiple flues. Each flue connects a corresponding top hole of the top panel and a bottom hole of the bottom panel. The substrate is mounted on the bottom panel and has multiple independent through holes respectively corresponding to the flues. The LED assemblies are respectively mounted on the substrate between two adjacent through holes. The rotatable mounting assemblies are respectively connected to two ends of the heat dissipating bracket, wherein the heat dissipating bracket is adapted to change an illuminating direction of the LED assemblies by rotating with the rotatable mounting assemblies. With the heat dissipating bracket and the rotatable mounting assemblies, the LED module obtains good heat-dissipating efficiency and optimal light distribution.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: October 12, 2010
    Assignee: Pan-Jit International Inc.
    Inventors: Tsu Lee, Feng Ma, Jin-Yun Yang, Zhong-Lin Tang, Lei Zhao
  • Patent number: D636106
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: April 12, 2011
    Assignee: Pan-Jit International Inc.
    Inventors: Tsu Lee, Zhong-Lin Tang, Lei Zhao, Chun Kin Patrick Chan, Feng Ma, Jin-Yun Yang
  • Patent number: D678579
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: March 19, 2013
    Assignee: Pan-Jit International Inc.
    Inventors: Tsu Lee, Zhong-Lin Tang, Lei Zhao, Chun Kin Patrick Chan, Feng Ma, Jin-Yun Yang