Abstract: The present disclosure relates to a manufacturing and measuring system for semiconductor structures on a wafer. The system includes a process chamber and a measuring device. The process chamber is configured to perform operations of forming a first fin array in a bank of a die of a wafer and forming a second fin array on the first fin array. The measuring device is configured to perform a pattern wafer geometer (PWG) measuring on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array, and further configured to determine a status of wafer according to the displacement.

Abstract: A measuring method for measuring an overlay shift between two wafers, comprising: providing a previous wafer layer, a to-be-measured wafer layer and a measuring circuit layer, wherein each of the previous wafer layer and the to-be-measured wafer layer comprises a first group of dies; measuring, by a plurality of probes of the measuring circuit layer, the first group of dies of the to-be-measured wafer layer; generating a measurement result according to at least the measuring to the first group of dies; and comparing the measurement result with a standard data to determine the overlay shift between the previous wafer layer and the to-be-measured wafer layer, wherein the to-be-measured wafer layer is between the previous wafer layer and the measuring circuit layer and is connected to the previous wafer layer and the measuring circuit layer.

Abstract: A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.

Abstract: The present disclosure provides a manufacturing method for semiconductor structures. The method includes the following operations: receiving a wafer having a plurality of dies; respectively forming a plurality of semiconductor structures in a plurality of banks in each of the plurality of dies, wherein each of the semiconductor structure includes a first fin array and a second fin array disposed above the first fin array; performing a PWG measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and according to the displacement, determining a status of wafer.

Abstract: The present disclosure relates to a manufacturing and measuring system for semiconductor structures on a wafer. The system includes a process chamber and a measuring device. The process chamber is configured to perform operations of forming a first fin array in a bank of a die of a wafer and forming a second fin array on the first fin array. The measuring device is configured to perform a pattern wafer geometer (PWG) measuring on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array, and further configured to determine a status of wafer according to the displacement.

Abstract: A method of semiconductor overlay measuring includes following operations. Provide a test substrate. Conductive structures are located in the test substrate and exposed from a top surface of the test substrate. Positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate. Mark first marks corresponding to the exposed conductive structures on the first image. Form a test capping layer with capacitor openings on the top surface of the test substrate. Move the test substrate to the standard position and capturing a second image of a top surface of the test capping layer. Identify the capacitor openings on the second image with second marks. Compare the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.