Abstract: A method of adjusting the size of a photomask pattern is provided. First, the original coordinate is converted. Then the length and width of the original pattern are converted. Next, the size difference caused by the coordinate conversion is corrected according to the result of the length and width conversion.

Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.

Abstract: A method of adjusting the size of a photomask pattern is provided. First, the original coordinate is converted. Then the length and width of the original pattern are converted. Next, the size difference caused by the coordinate conversion is corrected according to the result of the length and width conversion.

Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.

Abstract: The two dimensional intensity profile of radiation applied to a semiconductor wafer during photolithography is controlled by passing the radiation beam through an attenuating member before the beam is imaged by a mask onto the wafer. The attenuating member is preferably ring shaped and is formed of a semi-transparent material such as Mo Bi Si O4, or a material that is partially reflective of the radiation.

Abstract: A method for making advanced guard rings in a stacked film on logic/merged DRAM circuits using a novel mask design is achieved. After forming a patterned amorphous silicon (a-Si) layer that has blanket portions over the logic region, a stacked film is deposited over the a-Si layer and extending over the edge and on the memory region. A first photoresist etch mask is used to pattern FET gate electrodes in the stacked film, and the etch mask includes a portion having a minimum width W over the edge of the a-Si layer to form a wide guard ring. This wide guard ring replaces a narrow guard ring that inadvertently forms during conventional processing and that is susceptible to peeling and particle contamination of the wafer. A second photoresist etch mask is used to pattern the a-Si layer to form FET gate electrodes over the logic region.

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.