Patents by Inventor Tsubasa Harada

Tsubasa Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8552516
    Abstract: According to one embodiment, a solid state image capture device includes a multilayered interconnect layer, a semiconductor substrate, a pillar diffusion layer and an insulating member. The multilayered interconnect layer includes an interconnect. The semiconductor substrate is provided on the multilayered interconnect layer and the semiconductor substrate has a through-trench. The pillar diffusion layer is formed in the semiconductor substrate around the through-trench. In addition, an insulating member is filled into the through-trench.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Murakoshi, Tsubasa Harada
  • Patent number: 7977141
    Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsubasa Harada, Atsushi Murakoshi
  • Publication number: 20110084350
    Abstract: According to one embodiment, a solid state image capture device includes a multilayered interconnect layer, a semiconductor substrate, a pillar diffusion layer and an insulating member. The multilayered interconnect layer includes an interconnect. The semiconductor substrate is provided on the multilayered interconnect layer and the semiconductor substrate has a through-trench. The pillar diffusion layer is formed in the semiconductor substrate around the through-trench. In addition, an insulating member is filled into the through-trench.
    Type: Application
    Filed: July 2, 2010
    Publication date: April 14, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi MURAKOSHI, Tsubasa Harada
  • Publication number: 20100181637
    Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.
    Type: Application
    Filed: August 31, 2009
    Publication date: July 22, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsubasa Harada, Atsushi Murakoshi
  • Patent number: 7126178
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: October 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
  • Publication number: 20060097303
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Application
    Filed: December 21, 2005
    Publication date: May 11, 2006
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
  • Patent number: 6982198
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: January 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
  • Patent number: 6946699
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: September 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
  • Publication number: 20050170582
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Application
    Filed: March 2, 2005
    Publication date: August 4, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
  • Publication number: 20050167720
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Application
    Filed: March 2, 2005
    Publication date: August 4, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao
  • Publication number: 20040106254
    Abstract: A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.
    Type: Application
    Filed: April 10, 2003
    Publication date: June 3, 2004
    Inventors: Takeo Furuhata, Ichiro Mizushima, Akiko Sekihara, Motoya Kishida, Tsubasa Harada, Takashi Nakao