Patents by Inventor Tsubasa Imamura
Tsubasa Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9502470Abstract: According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.Type: GrantFiled: March 10, 2015Date of Patent: November 22, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Takahashi, Toshiyuki Sasaki, Tsubasa Imamura
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Patent number: 9384980Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask.Type: GrantFiled: September 9, 2014Date of Patent: July 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhito Yoshimizu, Mitsuhiro Omura, Hisashi Okuchi, Satoshi Wakatsuki, Tsubasa Imamura
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Patent number: 9373523Abstract: A semiconductor device manufacturing method includes performing reactive ion etching of the film containing a metal disposed on the bottom of the first groove and the film containing a metal disposed on the bottom of the second groove under a same condition in a state where the substrate is heated to the target temperature.Type: GrantFiled: February 9, 2015Date of Patent: June 21, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keisuke Kikutani, Tsubasa Imamura
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Publication number: 20160079076Abstract: According to one embodiment, a pattern forming method is provided. The method includes making a template touch resist material to form a first resist layer. The template has a recess/protrusion pattern. The method includes making a template touch resist material to form a second resist layer. The template has a recess/protrusion pattern. The method includes etching a processing object having the first resist layer and the second resist layer formed thereon. In forming the first resist layer, the template is kept at a position where a distance between a protrusion of the recess/protrusion pattern and the processing object takes on a first length. In forming the second resist layer, the template is kept at a position where a distance between a protrusion of the recess/protrusion pattern and the processing object takes on a second length. The second length is different from the first length.Type: ApplicationFiled: December 17, 2014Publication date: March 17, 2016Inventors: HIROSHI YAMAMOTO, TSUBASA IMAMURA, MITSUHIRO OMURA
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Publication number: 20160071741Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer made of a material different from a material of an etching target layer above the etching target layer. The method includes forming a plurality of first mask holes, sacrificial films being buried in the first mask holes, and a plurality of second mask holes, in the mask layer. The method includes retreating the sacrificial films in a depth direction of the first mask holes to expose portions of the first mask holes onto the sacrificial films. The method includes etching the etching target layer under the second mask holes using the mask layer and the sacrificial films as a mask, to form holes in the etching target layer under the second mask holes.Type: ApplicationFiled: March 10, 2015Publication date: March 10, 2016Inventors: Tsubasa IMAMURA, Mitsuhiro OMURA
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Publication number: 20160071739Abstract: A semiconductor device manufacturing method includes performing reactive ion etching of the film containing a metal disposed on the bottom of the first groove and the film containing a metal disposed on the bottom of the second groove under a same condition in a state where the substrate is heated to the target temperature.Type: ApplicationFiled: February 9, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keisuke KIKUTANI, Tsubasa Imamura
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Publication number: 20160035792Abstract: According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.Type: ApplicationFiled: March 10, 2015Publication date: February 4, 2016Inventors: Atsushi TAKAHASHI, Toshiyuki Sasaki, Tsubasa Imamura
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Publication number: 20160005604Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask.Type: ApplicationFiled: September 9, 2014Publication date: January 7, 2016Inventors: Yasuhito YOSHIMIZU, Mitsuhiro OMURA, Hisashi OKUCHI, Satoshi WAKATSUKI, Tsubasa IMAMURA
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Patent number: 9111875Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.Type: GrantFiled: March 10, 2014Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Yamamoto, Tsubasa Imamura, Hisataka Hayashi, Mitsuhiro Omura
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Patent number: 9105584Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.Type: GrantFiled: January 3, 2014Date of Patent: August 11, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Omura, Toshiyuki Sasaki, Tsubasa Imamura, Kazuhisa Matsuda
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Publication number: 20150064913Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.Type: ApplicationFiled: January 3, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: MITSUHIRO OMURA, Toshiyuki SASAKI, Tsubasa IMAMURA, Kazuhisa MATSUDA
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Publication number: 20150011089Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.Type: ApplicationFiled: March 10, 2014Publication date: January 8, 2015Inventors: Hiroshi Yamamoto, Tsubasa Imamura, Hisataka Hayashi, Mitsuhiro Omura
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Publication number: 20140083977Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.Type: ApplicationFiled: September 25, 2013Publication date: March 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akio UI, Hisataka Hayashi, Kazuhiro Tomioka, Hiroshi Yamamoto, Tsubasa Imamura
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Patent number: 8536061Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).Type: GrantFiled: March 11, 2011Date of Patent: September 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hisataka Hayashi, Yusuke Kasahara, Tsubasa Imamura
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Publication number: 20120034785Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).Type: ApplicationFiled: March 11, 2011Publication date: February 9, 2012Inventors: Hisataka HAYASHI, Yusuke Kasahara, Tsubasa Imamura
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Patent number: 7902076Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a porous film above a semiconductor substrate; forming an altered layer by applying alteration treatment to a first pattern region of the porous film up to a predetermined depth; forming a first concave portion by etching a second pattern region to a depth deeper than the predetermined depth, the second pattern region at least partially overlapping the first pattern region of the porous film having the altered layer formed therein; and forming a second concave portion by selectively removing the altered layer from the porous film after forming the first concave portion.Type: GrantFiled: June 3, 2009Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Tsubasa Imamura
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Publication number: 20100003818Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a porous film above a semiconductor substrate; forming an altered layer by applying alteration treatment to a first pattern region of the porous film up to a predetermined depth; forming a first concave portion by etching a second pattern region to a depth deeper than the predetermined depth, the second pattern region at least partially overlapping the first pattern region of the porous film having the altered layer formed therein; and forming a second concave portion by selectively removing the altered layer from the porous film after forming the first concave portion.Type: ApplicationFiled: June 3, 2009Publication date: January 7, 2010Inventor: Tsubasa IMAMURA