Patents by Inventor Tsubasa INOUE
Tsubasa INOUE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11715795Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: GrantFiled: October 5, 2021Date of Patent: August 1, 2023Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
-
Patent number: 11637176Abstract: Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm?Lxr?0.20 ?m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.Type: GrantFiled: July 7, 2022Date of Patent: April 25, 2023Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Hironao Nakamura, Ryosuke Okawa, Tsubasa Inoue, Akira Kimura, Eiji Yasuda
-
Patent number: 11626399Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: GrantFiled: February 1, 2022Date of Patent: April 11, 2023Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue
-
Publication number: 20230101684Abstract: Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm?Lxr?0.20 ?m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.Type: ApplicationFiled: July 7, 2022Publication date: March 30, 2023Inventors: Hironao NAKAMURA, Ryosuke Okawa, Tsubasa Inoue, Akira Kimura, Eiji Yasuda
-
Publication number: 20220157806Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Kazuma YOSHIDA, Ryosuke Okawa, Tsubasa Inoue
-
Patent number: 11282834Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: GrantFiled: April 12, 2021Date of Patent: March 22, 2022Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue
-
Publication number: 20220029016Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Ryosuke OKAWA, Toshikazu IMAI, Kazuma YOSHIDA, Tsubasa INOUE, Takeshi IMAMURA
-
Patent number: 11171234Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: GrantFiled: August 6, 2020Date of Patent: November 9, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
-
Publication number: 20210233905Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Kazuma Yoshida, Ryosuke OKAWA, Tsubasa INOUE
-
Patent number: 11049856Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: GrantFiled: January 25, 2019Date of Patent: June 29, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue
-
Patent number: 10893616Abstract: Disclosed is a production method of a multi-layered printed wiring board, including the following steps 1 to 3: Step 1: a step of laminating, on a substrate with inner layer circuit, a metal foil with adhesive layer including a support, a metal foil having a thickness of 3 ?m or less and ? or less relative to the thickness of the inner layer circuit, and an organic adhesive layer having a thickness of 10 ?m or less in this order, via an organic insulating resin layer such that the organic insulating resin layer and the organic adhesive layer are opposed to each other, and then releasing the support to form a laminated sheet (a) having the metal foil as an outer layer metal foil layer; Step 2: a step of irradiating the laminated sheet (a) with a laser to bore the outer layer metal foil layer, the organic adhesive layer, and the organic insulating resin layer to form a bored laminated sheet (b) having a blind via hole; and Step 3: a step of forming an outer layer circuit connected with the inner layer circuiType: GrantFiled: August 10, 2016Date of Patent: January 12, 2021Assignee: Showa Denko Materials Co., Ltd.Inventors: Hitoshi Onozeki, Tsubasa Inoue, Katsuji Yamagishi, Hiroshi Shimizu
-
Publication number: 20200388609Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.Type: ApplicationFiled: January 25, 2019Publication date: December 10, 2020Inventors: Kazuma YOSHIDA, Ryosuke OKAWA, Tsubasa INOUE
-
Publication number: 20200365729Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Inventors: Ryosuke OKAWA, Toshikazu IMAI, Kazuma YOSHIDA, Tsubasa INOUE, Takeshi IMAMURA
-
Publication number: 20180235090Abstract: Disclosed is a production method of a multi-layered printed wiring board, including the following steps 1 to 3: Step 1: a step of laminating, on a substrate with inner layer circuit, a metal foil with adhesive layer including a support, a metal foil having a thickness of 3 ?m or less and ? or less relative to the thickness of the inner layer circuit, and an organic adhesive layer having a thickness of 10 ?m or less in this order, via an organic insulating resin layer such that the organic insulating resin layer and the organic adhesive layer are opposed to each other, and then releasing the support to form a laminated sheet (a) having the metal foil as an outer layer metal foil layer; Step 2: a step of irradiating the laminated sheet (a) with a laser to bore the outer layer metal foil layer, the organic adhesive layer, and the organic insulating resin layer to form a bored laminated sheet (b) having a blind via hole; and Step 3: a step of forming an outer layer circuit connected with the inner layer circuiType: ApplicationFiled: August 10, 2016Publication date: August 16, 2018Inventors: Hitoshi ONOZEKI, Tsubasa INOUE, Katsuji YAMAGISHI, Hiroshi SHIMIZU
-
Patent number: D934820Type: GrantFiled: October 24, 2019Date of Patent: November 2, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
-
Patent number: D937232Type: GrantFiled: July 30, 2021Date of Patent: November 30, 2021Assignee: Nuvoton Technology Corporation JapanInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
-
Patent number: D937233Type: GrantFiled: July 30, 2021Date of Patent: November 30, 2021Assignee: Nuvoton Technology Corporation JapanInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura
-
Patent number: D938925Type: GrantFiled: October 24, 2019Date of Patent: December 21, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Ryosuke Okawa, Toshikazu Imai, Kazuma Yoshida, Tsubasa Inoue, Takeshi Imamura