Abstract: An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the plating solution are connected to an anode and the body to be plated is connected to a cathode of a power supply.

Abstract: An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the plating solution are connected to an anode and the body to be plated is connected to a cathode of a power supply.

Abstract: An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the plating solution are connected to an anode and the body to be plated is connected to a cathode of a power supply.

Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.

Abstract: An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the plating solution are connected to an anode and the body to be plated is connected to a cathode of a power supply.

Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.

Abstract: A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhesive layer and formed harder than the insulating adhesive layer, wires for connecting pads on the semiconductor chip with connecting terminals on the tape substrate, a sealing portion formed by sealing the semiconductor chip with resin, and plural solder balls provided on a back of the tape substrate. A die bonding layer for fixing the semiconductor chip thereto is composed of an insulating adhesive layer and the insulating sheet member laminated thereto. The die bonding layer is formed thick by such a multi-layer structure, whereby the resin balance of the surface and back of the semiconductor chip is improved to prevent warping of a package and improve the mounting temperature cyclicity and reflow characteristic.

Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.

Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.

Abstract: A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhesive layer and formed harder than the insulating adhesive layer, wires for connecting pads on the semiconductor chip with connecting terminals on the tape substrate, a sealing portion formed by sealing the semiconductor chip with resin, and plural solder balls provided on a back of the tape substrate. A die bonding layer for fixing the semiconductor chip thereto is composed of an insulating adhesive layer and the insulating sheet member laminated thereto. The die bonding layer is formed thick by such a multi-layer structure, whereby the resin balance of the surface and back of the semiconductor chip is improved to prevent warping of a package and improve the mounting temperature cyclicity and reflow characteristic.

Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.

Abstract: There is provided a semiconductor chip mounting area for mounting a semiconductor chip, and the points of the inner leads are made to come closer to the semiconductor chip mounting area by arranging the points of the inner leads at equal intervals over the whole periphery of the semiconductor chip mounting area. The points of the inner leads are arranged along the whole periphery of the semiconductor chip mounting area, and the lead pitch at the points of the inner leads corresponding to a corner portion of the semiconductor chip mounting area is made wider than the lead pitch of the other inner lead points.