Patents by Inventor Tsugihiko Ohno

Tsugihiko Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6843413
    Abstract: This invention relates to a method for providing information by using a contactless IC (integrated circuit) card and a device for providing information. It is an object of this invention to obtain mass data and data created dynamically, and also to solve troublesome work of updating data in the contactless IC card. Data 9 of location information for accessing data 8 of external information are stored in a contactless IC card 7. A device 10 for providing information reads the data 9 of location information and accesses the data 8 of external information based on the data 9 of location information read.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: January 18, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohisa Yamaguchi, Tsugihiko Ohno, Norihito Takatori
  • Publication number: 20040015560
    Abstract: This invention relates to a method for providing information by using a contactless IC (integrated circuit) card and a device for providing information. It is an object of this invention to obtain mass data and data created dynamically, and also to solve troublesome work of updating data in the contactless IC card. Data 9 of location information for accessing data 8 of external information are stored in a contactless IC card 7. A device 10 for providing information reads the data 9 of location information and accesses the data 8 of external information based on the data 9 of location information read.
    Type: Application
    Filed: April 14, 2003
    Publication date: January 22, 2004
    Inventors: Tomohisa Yamaguchi, Tsugihiko Ohno, Norihito Takatori
  • Patent number: 5812757
    Abstract: A fault recovery process of a computer is provided for removing a fault from the system as soon as possible, minimizing the secondary fault and improving the availability of the system. In a reliable computer, which includes a system bus, a main memory connected to the system bus, and at least one processing board connected to the system bus, at least one processing board executes the same instructions by n (n>=3) processing units having cache memories respectively. When one of the processing units of the processing board becomes faulty, the other processing units continue executing the processes, which are being executed by the faulty processing board, and then, the processes to be registered in the faulty processing board, are succeeded by other processing boards.
    Type: Grant
    Filed: July 5, 1996
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiromu Okamoto, Takashi Tanabe, Kaoru Abe, Tsugihiko Ohno, Toyohito Hatashita, Toshihisa Kamemaru, Norihisa Kaneda, Mamoru Katoh, Masakazu Soga
  • Patent number: 5577199
    Abstract: This invention provides a majority circuit, connecting a plurality of processing units. The majority circuit can detect a single error or multiple errors, and sets the majority output signal to an ineffective level when multiple errors are detected. The majority circuit includes comparators, each comparing two outputs of three processing units, and the error detector recognizes the error status and outputs the single error signal and the multiple error signal accordingly. The majority circuit also includes a selector, which selects the output of a normal processing unit, when the normal processing unit can be specified based on the comparison result. The selector changes the output to a predetermined level, when the normal processing unit cannot be specified.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: November 19, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Tanabe, Toshihisa Kamemaru, Mamoru Katoh, Tsugihiko Ohno, Toyohito Hatashita, Kaoru Abe