Abstract: Multiple CPU's are assigned to multiple tasks on a one-to-one basis and execute corresponding tasks under the control of an operating system. Each of the CPU has a transmitter and a receiver. Each transmitter of the CPU's is connected to the receivers in the remainder of the CPU's. The CPU's are arranged so that, in response to the execution of an interrupt instruction in one of a number of tasks, the transmitter of the corresponding CPU outputs an interrupt request to each of the receivers of the remainder of the CPU's. Thus, the remainder of the tasks are suspended. An interrupt controller which is included in the operating system, takes over the control of the CPU's and the tasks in response to the transmission and the reception of the interrupt request by the above-mentioned CPU. A task status determining program initiates to examine each status of said tasks when the interrupt controller ascertains suspension of each of the tasks.