Abstract: A non-transitory computer-readable storage medium storing a threshold determination program that causes a processor included in a computer to execute a process, the process includes quantitating a plurality of numerical values of a quantization target using a variable representing a candidate of a threshold, and determining the threshold based on a quantization error for each of the plurality of numerical values, the quantization error is specified based on the quantitating.

Abstract: An apparatus serves as at least one of a plurality of information processing devices each including a group of arithmetic processors, where the plurality of information processing devices are configured to perform parallel processing by using calculation result data of the groups of arithmetic processors included in the plurality of information processing devices. The apparatus includes a memory configured to store bandwidth information indicating a communication bandwidth with which an arithmetic processor included in the groups of arithmetic processors communicate with another arithmetic processor included in the groups of arithmetic processors. For a source arithmetic processor that is any one of the groups of arithmetic processors, the apparatus determines a destination arithmetic processor that is one of the groups of arithmetic processors to which the calculation result data of the source arithmetic processor is to be transferred, based on the bandwidth information stored in the memory.

Abstract: An apparatus includes a processor coupled to a memory and configured to extract a class in which a constructor or an assignment operator included in source code or a combination of the constructor and the operator is used, identify a call to the constructor or operator or the combination, calculate the number of times of access to member variables, indicated in the call identified and a periphery of the call; compare the number, calculated, of times of the access with the number of times of memory access, and generate intermediate code having, added thereto, information to be used to execute a process for copying the constructor or the operator or the combination in units of member variables, and generate intermediate code having information added thereto based on the call when the number, calculated, of times of the access is smaller than the number of times of the memory access.

Abstract: A machine learning method, using a neural network as a model, executed by a computer, the machine learning method including dividing a first batch data into a plurality of pieces of second batch data, the first batch data being a set of sample data to be input into the model in a machine learning, allocating the plurality of pieces of second batch data to a plurality of computers, the model having a specified layered structure and a specified parameter of the neural network being applied to the plurality of computers, making the plurality of computers to execute the machine learning based on the plurality of allocated second batch data, obtaining, from each of the plurality of computers, a plurality of correction amounts of the parameter derived by the executed machine learning, and correcting the model by modifying the specified parameter in accordance with the plurality of correction amounts.

Abstract: The parallel information processing apparatus includes a plurality of nodes each including a first processor and a second processor. The first processor is configured to execute a computation process using a coefficient for a target data, computing a coefficient variation based on a result of the computation process, transferring the computed coefficient variation to the second processor and requesting the second processor to execute a transfer/receipt process. The second processor is configured to transmit the coefficient variation transferred from the first processor to another node and receive the coefficient variation computed by another node and integrate the coefficient variation transferred from the first processor and the coefficient variation computed by another node. At least one of the first processor and the second processor updates the coefficient to be used for the computation process from next time onward based on the integrated coefficient variation.

Abstract: An apparatus includes a processor coupled to a memory and configured to extract a class in which a constructor or an assignment operator included in source code or a combination of the constructor and the operator is used, identify a call to the constructor or operator or the combination, calculate the number of times of access to member variables, indicated in the call identified and a periphery of the call; compare the number, calculated, of times of the access with the number of times of memory access , and generate intermediate code having, added thereto, information to be used to execute a process for copying the constructor or the operator or the combination in units of member variables, and generate intermediate code having information added thereto based on the call when the number, calculated, of times of the access is smaller than the number of times of the memory access.

Abstract: A disclosed hash generation method includes: calculating a hash matrix for identifying original data, which corresponds to a product multiplied by a partial hash matrix of a last block of plural blocks divided from the original data, from a product for each of blocks other than the last block, which is calculated by multiplying from a partial hash matrix of a first block of the plural blocks up to a partial hash matrix of the block; and calculating a hash matrix for identifying changed data, by multiplying a product of a product multiplied lastly by a partial hash matrix of a block immediately before a changed block and a partial hash matrix of the changed block by an inverse matrix of a product multiplied lastly by a partial hash matrix of an unchanged original block and a product multiplied lastly by a partial hash matrix of the last block.

Abstract: An information processing apparatus includes a memory; and one or more processors coupled to the memory and configured to specify a loop portion in which computation regarding a first expression, which performs a contraction operation with respect to a first variable, is repeated, in a first program code of software, generate a first code in which computation regarding a second expression, which performs a contraction operation on a sub-expression of the first expression with respect to a second variable, is repeated and a second code in which computation regarding a third expression, where the sub-expression of the first expression is replaced with the second variable, is repeated, and output a second program code in which the loop portion of the first program code is transformed into the first code and the second code.

Abstract: A method includes: reading, when each of a plurality of pieces of data is set as target data to be grouped and the target data is grouped based on boundary value of a root node in a binary tree, the target data from the plurality of pieces of data, specifying a temporary maximum value that indicates a maximum value among the target data and data already grouped, and a temporary minimum value that indicates a minimum value among the target data to be grouped and the data already grouped; specifying a maximum value and a minimum value of the plurality of pieces of data by updating the temporary maximum value and the temporary minimum value; and dividing the plurality of pieces of data based on a boundary value between the maximum value and the minimum value of the plurality of pieces of data among the plurality of boundary values.

Abstract: An arithmetic processing apparatus includes a plurality of arithmetic cores configured to execute threads in parallel, and a control unit configured to cause the arithmetic core to execute a reduction operation for data of the threads having the same storage area to which data is written per a predetermined number of threads in order to add data obtained by the reduction operation to data within a corresponding storage area by an atomic process.

Abstract: A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.

Abstract: An arithmetic processing apparatus includes a plurality of arithmetic cores configured to execute threads in parallel, and a control unit configured to cause the arithmetic core to execute a reduction operation for data of the threads having the same storage area to which data is written per a predetermined number of threads in order to add data obtained by the reduction operation to data within a corresponding storage area by an atomic process.

Abstract: An information processing apparatus includes a first arithmetic processing apparatus, a second arithmetic processing apparatus, and a control unit that controls the first arithmetic apparatus and the second arithmetic apparatus, wherein the control unit causes each of the first arithmetic processing apparatus and the second arithmetic processing apparatus to execute a first data processing common to the first and the second arithmetic processing apparatuses, and the control unit causes the second arithmetic processing apparatus to stop the first data processing when the first data processing executed by the first arithmetic processing apparatus is completed earlier than the first data processing executed by the second arithmetic processing apparatus.

Abstract: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.

Abstract: A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.

Abstract: A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration.

Abstract: A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.

Abstract: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.

Abstract: A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration.

Abstract: A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.