Abstract: The present invention concerns a mobile packet communication system that supports data communications, including Internet communications, in a high-speed mobile communication system such as a cellular communication network, and integrates a mobile network and a fixed network on a common platform while providing the capability to select an optimum route.

Abstract: The present invention provides a mobile communication network system comprising a first mobile communication network having a plurality of routers, a second mobile communication network having a plurality of routers, and a mobile communication terminal. A router located in an end section of a communication area of the first mobile communication network sends an end message indicating that it is located in the end section, to the mobile communication terminal. The terminal initiates communications with a router of the second mobile communication network, whilst the terminal is communicating with the router located in the end section, upon receiving the end message sent by the router located in the end section.

Abstract: A gate node reports current position information of a mobile terminal managed by the gate node itself to a communicating edge node which routes a packet destined for the mobile terminal to the gate node. The communicating edge node carries out routing of the packet destined for the mobile terminal to a resident edge node based on the reported cache information in place of the gate node. This achieves high-speed handover and route optimization free from a limitation to a packet transfer route in a packet communication system.

Abstract: A short cell multiplexer includes a sequence designating unit, in which reading intervals corresponding to QOS classes are set in respective reading interval setting registers. A counter memory is stored with the number of timings at which the short cells can be read. The sequence designating unit specifies the QOS class in which the number of timings reaches the reading interval on the basis of the reading interval and the number of timings, and gives to a reading unit an indication of reading the short cell belonging to this class.

Abstract: A short cell multiplexer includes a sequence designating unit, in which reading intervals corresponding to QOS classes are set in respective reading interval setting registers. A counter memory is stored with the number of timings at which the short cells can be read. The sequence designating unit specifies the QOS class in which the number of timings reaches the reading interval on the basis of the reading interval and the number of timings, and gives to a reading unit an indication of reading the short cell belonging to this class.

Abstract: An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

Abstract: The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

Abstract: A mobile node adapted router and home agent router operating by the IPv6 protocol able to shorten the time required for updating the current address of the mobile node and increase the speed of switching of the transfer route and providing a transfer route not passing through a home agent every time for a node not supporting this protocol, provided with a memory unit for storing a current address of a mobile node which the correspondent node should store instead of the correspondent node and a transfer unit for referring to the memory unit when receiving a packet transmitted to the home address of the mobile node, converting it to the current address, and transmitting the packet.

Abstract: In a node device which is part of a communication system with a terminal and a location registering server, a node device on a receiving side transfers, to a destination node device, a received inter-node packet, based on destination terminal location information stored in its storage portion or based on a location registering server, directly or through other devices, or the destination node device notifies a former node device (on the receiving side) of an address of its own device and the destination terminal directly or through other devices. Also, the node device on the receiving side or the destination node device notify a source node device of the address of the destination node device and the destination terminal directly or through other devices, based on a predetermined address stored in the storage portion of the terminal, the node device, or the location registering server.

Abstract: The quality classes of arriving short cells and the ATM virtual connections to be multiplexed are identified based on the CIDs of those short cells. Those short cells are written into FIFO memories corresponding to the ATM virtual connections and quality classes. A VC specification control section specifies one ATM virtual connection for each ATM cell sending timing. At this time, a sequence specification control section specifies one or more quality classes in sequence. A readout control section reads one or more short cells out from the FIFO memory in accordance with the specified ATM virtual connection and quality class, stores them in one ATM cell and sends the ATM cell to the ATM virtual connection specified by the VC specification control section.

Abstract: To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length.

Abstract: A cell assembly and multiplexing device includes short cell assembly parts which store input information received via respective input lines and add short cell headers to the input information so that short cells having the short cell headers are assembled, and a multiplexing part which arranges the short cells in given fields of standard cells having a given standard format and a fixed cell length and outputs the standard cells having the short cells to a transmission line.

Abstract: A storage unit includes an alarm state/timer table, an alarm state table, an alarm state OR-representation table, an alarm state change OR-representation table, an alarm state latch circuit, and a statistical information memory. A collection unit extracts the identifier and data from a cell that passes through a switching unit. An update unit updates associated data in the storage unit. A readout unit reads the updated data and sends it to a call processing processor. An address generation section selectively generates the address for data needing to be updated. An adjustment section forces the readout unit to wait until a cell slot arrives in which no data is updated.

Abstract: A storage unit includes an alarm state/timer table, an alarm state table, an alarm state OR-representation table, an alarm state change OR-representation table, an alarm state latch circuit, and a statistical information memory. A collection unit extracts the identifier and data from a cell that passes through a switching unit. An update unit updates associated data in the storage unit. A readout unit reads the updated data and sends it to a call processing processor. An address generation section selectively generates the address for data needing to be updated. An adjustment section forces the readout unit to wait until a cell slot arrives in which no data is updated.

Abstract: A liquid resin composition prepared by mixing an ionic material and/or a chargeable material into a thermosetting or thermoplastic resin is injected into a mold having a predetermined inner shape, and a DC voltage is applied to the liquid resin composition to concentrate the ionic material and/or chargeable material on a desired portion or to distribute the ionic material and/or chargeable material continuously. Thereafter, the resin composition is thermally cured when the resin composition contains the thermosetting resin, or the resin composition is hardened by cooling when the resin composition contains the thermoplastic resin, thereby obtaining a molding having a predetermined shape.

Abstract: A phase adjustment circuit uses a broad band circuit for processing a plurality of high speed highway data comprising m bit frames. The phase adjustment circuit provides a master frame pulse based on a frame pulse selected from respective frame pulses in the high speed highway and delayed in phase by the maximum amount and provides a master clock based on a high speed highway clock corresponding to the master frame pulse. The phase adjustment circuit receives a plurality of high speed highway data by using the master clock and the master frame pulse.

Abstract: An epoxy resin composition for cast molding which comprises:(A) an epoxy resin;(B) a curing agent;(C) cut fibers having distributions of 3 to 20 .mu.m in diameter and 3 to 1500 .mu.m in length;(D) inorganic powder having a size distribution of particles with 90% by weight or more of particles with particle sizes of 10 .mu.m or less and 50% by weight or more of particles with particle sizes of 5 .mu.m or less,the total amount of the components (C) and (D) formulated being 40 to 225 parts by volume per 100 parts by volume of the total amount of the components (A) and (B) formulated displays excellent crack resistance, strength as well as a low shrinkage characteristic and, good fluidity.