Patents by Inventor Tsuguo Ueda

Tsuguo Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5379245
    Abstract: A modular multiplying assembly and a multiply module for use in the multiplying assembly implemented by hard-wired circuits are disclosed. Each module calculates multiplication for operands of a decimal single digit and can receive a carry or carries from adjacent module or modules. Each of the modules is implemented by a memory member or a set of logic gates such as a programmable logic array. In case of module implemented by a set of logic gates, an extremely high-speed calculation is obtained.
    Type: Grant
    Filed: January 6, 1993
    Date of Patent: January 3, 1995
    Assignee: NEC Corporation
    Inventor: Tsuguo Ueda
  • Patent number: 5261028
    Abstract: A circuit for discriminating whether or not a given point exists within a predetermined linear area, comprises first and second registers for storing first and second boundary values defining the predetermined linear area. A first detection circuit receives the first boundary value and a value of the given point, and a second detection circuit receives the second boundary value and the value of the given point. Each of the first and second detection circuits generating a first signal indicating that the boundary value is not greater than the value of the given point, a second signal indicating that the boundary value is equal to the value of the given point, and a third signal indicating that the boundary value is greater than the value of the given point.
    Type: Grant
    Filed: August 30, 1990
    Date of Patent: November 9, 1993
    Assignee: NEC Corporation
    Inventor: Tsuguo Ueda