Patents by Inventor Tsuguto Maruko
Tsuguto Maruko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10433420Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.Type: GrantFiled: February 19, 2019Date of Patent: October 1, 2019Assignee: LAPIS Semiconductor Co., Ltd.Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Toru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
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Publication number: 20190261507Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.Type: ApplicationFiled: February 19, 2019Publication date: August 22, 2019Applicant: LAPIS Semiconductor Co., Ltd.Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Toru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
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Patent number: 10375819Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.Type: GrantFiled: February 20, 2018Date of Patent: August 6, 2019Assignee: LAPIS Semiconductor Co., Ltd.Inventors: Kentaro Toda, Kenji Arai, Manabu Miyazawa, Kenichiro Nagatomo, Touru Ueno, Tsuguto Maruko, Hirofumi Ogawa, Tetsuo Oomori
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Patent number: 10090263Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.Type: GrantFiled: June 7, 2017Date of Patent: October 2, 2018Assignee: ROHM CO., LTD.Inventor: Tsuguto Maruko
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Publication number: 20180242444Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.Type: ApplicationFiled: February 20, 2018Publication date: August 23, 2018Applicant: LAPIS Semiconductor Co., Ltd.Inventors: Kentaro TODA, Kenji ARAI, Manabu MIYAZAWA, Kenichiro NAGATOMO, Touru UENO, Tsuguto MARUKO, Hirofumi OGAWA, Tetsuo OOMORI
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Publication number: 20170271284Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.Type: ApplicationFiled: June 7, 2017Publication date: September 21, 2017Inventor: Tsuguto MARUKO
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Patent number: 9698111Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.Type: GrantFiled: July 28, 2016Date of Patent: July 4, 2017Assignee: ROHM CO., LTD.Inventor: Tsuguto Maruko
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Publication number: 20160336283Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Inventor: Tsuguto MARUKO
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Patent number: 9418957Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.Type: GrantFiled: May 19, 2015Date of Patent: August 16, 2016Assignee: ROHM CO., LTD.Inventor: Tsuguto Maruko
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Patent number: 9402130Abstract: A high-pass filter is configured to remove a low-pass filter component of a first channel audio signal and a low-pass filter component of a second channel audio signal. A control unit is configured to detect a wind noise magnitude based on at least one from among the first channel audio signal and the second channel audio signal, and to increase a cutoff frequency of the high-pass filter according to an increase in the wind noise magnitude thus detected. The control unit is configured to set the cutoff frequency of the high-pass filter to a predetermined minimum value fMIN when the wind noise magnitude thus detected is smaller than a predetermined minimum value, and to gradually increase the cutoff frequency when the wind noise magnitude becomes greater than the minimum value.Type: GrantFiled: September 12, 2013Date of Patent: July 26, 2016Assignee: ROHM CO., LTD.Inventor: Tsuguto Maruko
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Publication number: 20150340335Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.Type: ApplicationFiled: May 19, 2015Publication date: November 26, 2015Inventor: Tsuguto MARUKO
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Publication number: 20140079245Abstract: A high-pass filter is configured to remove a low-pass filter component of a first channel audio signal and a low-pass filter component of a second channel audio signal. A control unit is configured to detect a wind noise magnitude based on at least one from among the first channel audio signal and the second channel audio signal, and to increase a cutoff frequency of the high-pass filter according to an increase in the wind noise magnitude thus detected. The control unit is configured to set the cutoff frequency of the high-pass filter to a predetermined minimum value fMIN when the wind noise magnitude thus detected is smaller than a predetermined minimum value, and to gradually increase the cutoff frequency when the wind noise magnitude becomes greater than the minimum value.Type: ApplicationFiled: September 12, 2013Publication date: March 20, 2014Applicant: ROHM CO., LTD.Inventor: Tsuguto MARUKO
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Patent number: 8495270Abstract: A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal. In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal.Type: GrantFiled: June 14, 2011Date of Patent: July 23, 2013Assignee: Oki Semiconductor Co., Ltd.Inventor: Tsuguto Maruko
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Patent number: 8432194Abstract: A bias potential generating circuit includes a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ?? conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.Type: GrantFiled: October 21, 2010Date of Patent: April 30, 2013Assignee: Oki Semiconductor Co., Ltd.Inventors: Tsuguto Maruko, Kouhei Tanaka
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Patent number: 8103010Abstract: An apparatus for performing processing of an input acoustic signal to be reproduced by a loudspeaker, which generates a harmonic of a low pitch sound component equal to or lower than a predetermined low cutoff frequency, and generates a harmonic synthesized acoustic signal synthesizing the input signal with the harmonic. The apparatus generates an output acoustic signal which cuts off, from the harmonic synthesized acoustic signal, a low pitch sound component equal to or lower than the low cutoff frequency and a high pitch sound component equal to or higher than the high cutoff frequency. The apparatus sets a low and high cutoff frequencies in accordance with an output characteristic of a loudspeaker.Type: GrantFiled: May 20, 2008Date of Patent: January 24, 2012Assignee: Oki Semiconductor Co., Ltd.Inventors: Tsuguto Maruko, Naotaka Saito
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Publication number: 20110320853Abstract: A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminalType: ApplicationFiled: June 14, 2011Publication date: December 29, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Tsuguto Maruko
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Publication number: 20110095793Abstract: The present invention provides a bias potential generating circuit including: a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ?? conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.Type: ApplicationFiled: October 21, 2010Publication date: April 28, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventors: Tsuguto Maruko, Kouhei Tanaka
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Patent number: 7924190Abstract: A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.Type: GrantFiled: September 18, 2009Date of Patent: April 12, 2011Assignee: Oki Semiconductor Co., Ltd.Inventors: Tsuguto Maruko, Naotaka Saito
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Publication number: 20100073213Abstract: A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.Type: ApplicationFiled: September 18, 2009Publication date: March 25, 2010Inventors: Tsuguto Maruko, Naotaka Saito
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Patent number: 7557604Abstract: An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status at the mode setting terminal; and a control circuit that controls the logic holding circuit in accordance with a signal supplied to the chip selection terminal. Operation modes to be selected may be serial interface mode and parallel interface mode.Type: GrantFiled: May 3, 2005Date of Patent: July 7, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Shinsuke Onishi, Tsuguto Maruko