Patents by Inventor Tsuguyasu Hatsuda

Tsuguyasu Hatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5206825
    Abstract: This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: April 27, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naofumi Takagi, Tsuguyasu Hatsuda, Toru Kakiage, Takashi Taniguchi, Tamotsu Nishiyama
  • Patent number: 5153847
    Abstract: This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.
    Type: Grant
    Filed: October 16, 1990
    Date of Patent: October 6, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naofumi Takagi, Tsuguyasu Hatsuda, Toru Kakiage, Takashi Taniguchi, Tamotsu Nishiyama