Patents by Inventor Tsui-Yun LIAO

Tsui-Yun LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375638
    Abstract: A semiconductor substrate includes a first silicon substrate, an oxide layer, a second silicon substrate, and an epitaxial layer. The oxide layer is disposed on the first silicon substrate. The second silicon substrate is disposed on the oxide layer. The second silicon substrate has a thickness between 10 nm and 10 ?m. The epitaxial layer is disposed on the second silicon substrate.
    Type: Application
    Filed: September 29, 2020
    Publication date: December 2, 2021
    Inventors: Wen-Chung LI, Tsui-Yun LIAO
  • Patent number: 11145507
    Abstract: A method of forming a GaN film includes following steps. A silicon-on-insulator (SOI) substrate is provided. The SOI substrate includes a substrate, an insulator layer and a silicon layer. The insulator layer is disposed on the substrate and the silicon layer is disposed on the insulator layer. The silicon layer is pattered into a patterned silicon layer including a plurality of recessed features. Each recessed feature has a sidewall. A plurality of GaN structures are epitaxially grown from the sidewalls, and the GaN structures are separated from each other. The GaN structures are continuously epitaxially grown vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 12, 2021
    Assignee: WAFER WORKS CORPORATION
    Inventors: Ping-Hai Chiao, Wen-Chung Li, Tsui-Yun Liao
  • Publication number: 20210183652
    Abstract: A method of forming a GaN film includes following steps. A silicon-on-insulator (SOI) substrate is provided. The SOI substrate includes a substrate, an insulator layer and a silicon layer. The insulator layer is disposed on the substrate and the silicon layer is disposed on the insulator layer. The silicon layer is pattered into a patterned silicon layer including a plurality of recessed features. Each recessed feature has a sidewall. A plurality of GaN structures are epitaxially grown from the sidewalls, and the GaN structures are separated from each other. The GaN structures are continuously epitaxially grown vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Ping-Hai CHIAO, Wen-Chung LI, Tsui-Yun LIAO