Patents by Inventor Tsukasa Doi

Tsukasa Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130021397
    Abstract: An inkjet recording apparatus capable of determining an amount of bubbles in an ink flow path and performing suction recovery operation at an appropriate timing is provided. The inkjet recording apparatus includes a recording head including a nozzle for discharging ink and a flow path forming member forming an ink flow path for supplying the ink to the nozzle, a suction unit configured to suck the ink from the recording head, and a temperature detection unit configured to detect a temperature in the recording head. The inkjet recording apparatus includes a control unit configured, based on an amount of gas in the flow path forming member before the ink is filled in the ink flow path, and an amount of gas in equilibrium in the flow path forming member after the ink is filled in the ink flow path, to control the operation of the suction unit.
    Type: Application
    Filed: July 19, 2012
    Publication date: January 24, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tsukasa Doi, Kiichiro Takahashi, Akiko Maru, Takatoshi Nakano, Genji Inada, Satoshi Kimura
  • Publication number: 20120154476
    Abstract: The amount of ink wastage is reduced, even in a case wherein a predetermined amount of air bubbles has grown in a print head at a specific internal temperature and the growth has been settled, and thereafter the temperature in the print head is increased. A suction-based recovery control method, for an ink jet printing apparatus that includes a print head, a temperature detection unit, and a suction-based recovery unit, comprising: a temperature detection step; a temperature judgment step for judging whether the internal temperature of the print head is higher than a reference temperature that is determined based on internal temperatures of the print head that were previously employed; and a suction-based recovery step for permitting the suction-based recovery unit when it is determined at the temperature judgment step that the internal temperature of the print head is higher by the predetermined number of degrees or greater.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 21, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tsukasa Doi, Kiichiro Takahashi, Akiko Maru, Takatoshi Nakano, Hiroshi Taira
  • Publication number: 20110316906
    Abstract: An inkjet printing apparatus is provided that is capable of suppressing an increase in discarded ink by a restore operation of a restore unit. The apparatus is an inkjet printing apparatus that prints an image using a print head having a plurality of ejecting ports for ejecting ink and includes a restore unit that restores the ink ejection function of the print head, and a control unit that controls the restore unit so as to perform a restore operation depending on a parameter involving a growth rate of air bubbles existing inside the print head that is filled with ink.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 29, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroshi Taira, Kiichiro Takahashi, Akiko Maru, Tsukasa Doi
  • Patent number: 7402513
    Abstract: It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ?3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: July 22, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takanori Sonoda, Kazumasa Mitsumune, Kenichiroh Abe, Yushi Inoue, Tsukasa Doi
  • Publication number: 20060134865
    Abstract: According to the present invention, a method of manufacturing a semiconductor device which comprises a matrix of memory cells of the floating gate type is provided in which the silicon nitride layer is deposited as an etching stop layer on a control gate electrode for bottom borderless contact process with the threshold voltage of transistor arrangements being controlled not to change so that the productivity can remain not declined. In particular, the silicon nitride layer (115) is deposited as an etching stop layer on the control gate electrode (105) for bottom borderless contact process so that the concentration of hydrogen (H2) therein stays in a range from 1.5×1021 to 2.6×1021 atoms/cm3. Also, the silicon nitride layer (115) is deposited at a temperature of not higher than 700° C. by a low pressure CVD technique.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 22, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Inuzuka, Tsukasa Doi, Kazumasa Mitsumune
  • Publication number: 20050159015
    Abstract: It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ?3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.
    Type: Application
    Filed: January 12, 2005
    Publication date: July 21, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takanori Sonoda, Kazumasa Mitsumune, Kenichiroh Abe, Yushi Inoue, Tsukasa Doi
  • Publication number: 20050118833
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device suppressing the occurrence of voids in an insulating film. A method for manufacturing a semiconductor device according to the present invention comprises the steps of: (1) forming an insulating film 11 composed of a thin silicon nitride film on a semiconductor substrate 1 having at least a necessary element and a recessed part 6 so as to cover the recessed part 6; (2) modifying the surface of the insulating film 11; and (3) forming a BPSG film 15 as an interlayer insulation film on the insulating film. The occurrence of voids in the interlayer insulation film 15 is suppressed by the process for modifying the surface.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 2, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kazumasa Mitsumune, Tsukasa Doi, Yushi Inoue, Kenichirou Abe, Takanori Sonoda
  • Patent number: 6187648
    Abstract: A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the seco
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: February 13, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsukasa Doi, Shigeo Ohnishi, Katsuji Iguchi, Naoyuki Shinmura
  • Patent number: 5973400
    Abstract: A semiconductor device including, a wiring layer whose main component is copper being formed on a base via a barrier layer of amorphous tantalum carbide.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: October 26, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanori Murakami, Takeo Oku, Tsukasa Doi
  • Patent number: 5744394
    Abstract: A semiconductor device comprises a plurality of transistors A semiconductor device comprising a plurality of transistors formed on a semiconductor substrate and a metal interconnection layer connected to at least one of the transistors, wherein the metal interconnection layer is composed of a single layer or multi layers, the single layer or at least one layer of the multi layers being formed of copper or a copper alloy, and is connected to at least one transistor wholly or partially through a barrier layer; and at least one of the transistor is controlled on its threshold voltage by a selective ion implantation after formation of the metal interconnection layer.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: April 28, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuji Iguchi, Tsukasa Doi, Masanori Murakami, Takeo Oku
  • Patent number: 5459108
    Abstract: There is provided a semiconductor device manufacturing process which enables film deposition at low temperatures and can produce an interlayer insulating film of good quality which exhibits good surface smoothing effect. In the TEOS-O.sub.3 system normal pressure CVD process, film growth is carried out by adding to TEOS source a source containing nitrogen in its composition. For the source is used heptamethyl disilazane (chemical formula (CH.sub.3).sub.3 SiN(CH.sub.3)Si(CH.sub.3).sub.3), N, O-bis-trimethylsilyl acetamide (chemical formula (CH.sub.3)C(OSi(CH.sub.3).sub.3)(NSi(CH.sub.3).sub.3)) or tridimethylamino silane (chemical formula (CH.sub.3).sub.2 N).sub.3 SiN). Also, there is provided a semiconductor device manufacturing method which enables film deposition at a uniform growth rate irrespective of the substrate material and can produce a silicon oxide film of good quality which exhibits good surface smoothing effect. An organic source having an Si--N bond in its composition and O.sub.
    Type: Grant
    Filed: July 29, 1993
    Date of Patent: October 17, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsukasa Doi, Yukiko Mori
  • Patent number: 5241205
    Abstract: A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and th
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: August 31, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shin Shimizu, Katsuji Iguchi, Seizo Kakimoto, Tsukasa Doi