Abstract: An output buffer circuit includes first and second buffers, a slew rate control section and a first resistor. The first buffer has a pull-up transistor and a pull-down transistor to output an output signal to an output section from a first node located between the pull-up and pull-down transistors. The second buffer has complementary transistors and is provided in a front portion of the first buffer. A second node is located between the complementary transistors to be connected to the first node. The first resistor is connected between the second node and the output section to function as an output resistor of the second buffer. The first buffer complementarily operates in response to first and second control resistor respectively inputted to control electrodes of the pull-up and pull-down transistors, to output the output signal to the output section.