Patents by Inventor Tsukasa Hagura

Tsukasa Hagura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6717878
    Abstract: A first reference current having a first temperature characteristic is generated by a first reference current generating circuit (1) while a second reference current having a second temperature characteristic is generated by a second reference current generating circuit (2). A temperature characteristic multiplying circuit (3) amplifies the first reference current by using a current difference between the first and second reference currents to generate a reference current having a third temperature characteristic higher than the first temperature characteristic, so that a ring oscillator (X) determines a refresh period on the basis of the reference current.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: April 6, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Hagura, Masaki Tsukude
  • Patent number: 6693838
    Abstract: A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: February 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Hagura, Takafumi Takatsuka, Masaki Tsukude
  • Publication number: 20030198117
    Abstract: A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Hagura, Takafumi Takatsuka, Masaki Tsukude
  • Publication number: 20030185031
    Abstract: A first reference current having a first temperature characteristic is generated by a first reference current generating circuit (1) while a second reference current having a second temperature characteristic is generated by a second reference current generating circuit (2). A temperature characteristic multiplying circuit (3) amplifies the first reference current by using a current difference between the first and second reference currents to generate a reference current having a third temperature characteristic higher than the first temperature characteristic, so that a ring oscillator (X) determines a refresh period on the basis of the reference current.
    Type: Application
    Filed: October 3, 2002
    Publication date: October 2, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Hagura, Masaki Tsukude
  • Patent number: 6140862
    Abstract: A semiconductor integrated circuit has an internal power supply circuit which includes a differential amplifier, a driver transistor having its gate connected to an output terminal of the differential amplifier and is connected between an external power supply node and an internal power supply node, four transistors connected in parallel between the internal power supply node and a non-inversion input terminal of the differential amplifier, a first control circuit provided corresponding to two of the four transistors, and a second control circuit provided corresponding to remaining two of the transistors. The first control circuit includes a first fuse and a first signal generating circuit. The first signal generating circuit outputs a low level first control signal to the gate of the corresponding transistor when a first fuse is disconnected, and outputs a high level first control signal to the gate of the corresponding transistor when the first fuse is connected.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: October 31, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Hagura
  • Patent number: 5341340
    Abstract: A substrate bias generating circuit includes V.sub.BB generating circuits and a switching circuit. The switching circuit, in the standby period, applies an internal power supply voltage applied by an internal voltage down converting circuit to the V.sub.BB generating circuits. The switching circuit, in the active period, applies an external power supply voltage to the V.sub.BB generating circuits.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: August 23, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Hagura