Patents by Inventor Tsukasa Ichinose

Tsukasa Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8471379
    Abstract: A semiconductor device includes a semiconductor chip with first and second low noise amplifier for amplifying an inputted signal. The chip is mounted over a wiring substrate which includes first and second electrodes and first, second and third GND electrodes. The wiring substrate includes first and second conductor patterns, wherein the first conductor pattern electrically connects the first and second GND electrodes and surrounds the first and second electrodes in a plan view. The second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view. The first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Publication number: 20120126900
    Abstract: A semiconductor device includes a semiconductor chip with first and second low noise amplifier for amplifying an inputted signal. The chip is mounted over a wiring substrate which includes first and second electrodes and first, second and third GND electrodes. The wiring substrate includes first and second conductor patterns, wherein the first conductor pattern electrically connects the first and second GND electrodes and surrounds the first and second electrodes in a plan view. The second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view. The first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Inventors: Tadatoshi DANNO, Toru NAGAMINE, Hiroshi MORI, Tsukasa ICHINOSE
  • Patent number: 8115295
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Patent number: 7982301
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Publication number: 20110121443
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Application
    Filed: February 3, 2011
    Publication date: May 26, 2011
    Inventors: Tadatoshi DANNO, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Publication number: 20100001393
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Application
    Filed: September 15, 2009
    Publication date: January 7, 2010
    Inventors: Tadatoshi DANNO, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Patent number: 7608922
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: October 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Publication number: 20050263881
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 1, 2005
    Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose