Abstract: A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

Abstract: A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

Abstract: A video processing apparatus includes: an input section configured to receive an input signal as an input; a first FIFO configured to store input pixel data included in the input signal; a video processing section configured to generate output pixel data by performing predetermined video processing on the input pixel data; a second FIFO configured to store the output pixel data; a timer configured to measure a delay time starting from a time point at which a beginning location of the input pixel data is detected until a stored amount in the second FIFO becomes equal to or more than a predetermined threshold value; and a synchronization signal output section configured to output output synchronization signals used for outputting an output signal that is delayed by the delay time from the input signal.

Abstract: An image expansion apparatus includes a second order differential circuit, a multi-valued processing unit, a first determination unit, a selection unit, and an interpolation processing unit. The first determination unit compares respectively a plurality of fixed patterns, which is each assigned with an interpolation direction in accordance with an outline shape of an image, with spatial dispersion of an output of the multi-valued processing unit. The first determination unit determines a fixed pattern corresponding to the output. The first determination unit determines an interpolation direction assigned to the fixed pattern as a candidate of an interpolation direction for the outline shape. The selection unit selects an interpolation direction of a plurality of candidates of the interpolation direction for the outline shape. The interpolation processing unit generates an interpolation pixel to determine the pixel for the interpolation based on the interpolation direction selected by the selection unit.

Abstract: An image expansion apparatus includes a second order differential circuit, a multi-valued processing unit, a first determination unit, a selection unit, and an interpolation processing unit. The first determination unit compares respectively a plurality of fixed patterns, which is each assigned with an interpolation direction in accordance with an outline shape of an image, with spatial dispersion of an output of the multi-valued processing unit. The first determination unit determines a fixed pattern corresponding to the output. The first determination unit determines an interpolation direction assigned to the fixed pattern as a candidate of an interpolation direction for the outline shape. The selection unit selects an interpolation direction of a plurality of candidates of the interpolation direction for the outline shape. The interpolation processing unit generates an interpolation pixel to determine the pixel for the interpolation based on the interpolation direction selected by the selection unit.

Abstract: A digital broadcast receiving device includes a first processor for extracting added information, a storage device for storing the added information, and a second processor having a low power consumption mode and a normal power mode, for effecting the circuit control for the watching and listening operation according to a preset program and the added information. The first processor informs the second processor that the added information is extracted, the second processor changes the mode thereof to the normal power mode when it is informed from the first processor that the added information is extracted while it is set in the low power consumption mode in the standby state, writes the added information extracted by the first processor into the storage device, and changes the mode thereof into the low power consumption mode after completion of the write operation.