Patents by Inventor Tsukasa Nakai

Tsukasa Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11060990
    Abstract: A semiconductor measurement device includes an electrode provided in a semiconductor sample, and a probe contactable with the semiconductor sample. A driver moves a contact position of the probe with respect to the semiconductor sample. A power supply applies electric power between the probe and the electrode. A measurement operation portion measures a current flowing via the semiconductor sample between the probe and the electrode as a voltage applied between the probe and the electrode is changed, the measurement operation portion measuring the current flowing for each of plural measurement points of a surface of the semiconductor sample while causing the probe to scan the measurement points, or while sequentially bringing the probe into contact with the measurement points. A display displays a relationship between the voltage and the current measured at each of the measurement points.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Hirota, Tsukasa Nakai, Masako Kobayashi, Kazunori Harada
  • Patent number: 10545170
    Abstract: A measuring method of a scanning probe microscopy moves the probe from the first measuring point to the second measuring point while the probe has contact with the object to be measured and a pressing force weaker than the first pressing force is applied between the probe and the object to be measured after the measurement at the first measuring point has ended, applies the first pressing force between the probe and the object to be measured until the tip end position of the probe reaches the first distance in the depth direction from the upper surface of the object to be measured, and measures the physical property information of the object to be measured after the tip end position of the probe has reached the first distance in the depth direction from the upper surface of the object to be measured at the second measuring point.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Hirota, Kazunori Harada, Tsukasa Nakai
  • Publication number: 20190293586
    Abstract: A semiconductor measurement device includes an electrode provided in a semiconductor sample, and a probe contactable with the semiconductor sample. A driver moves a contact position of the probe with respect to the semiconductor sample. A power supply applies electric power between the probe and the electrode. A measurement operation portion measures a current flowing via the semiconductor sample between the probe and the electrode as a voltage applied between the probe and the electrode is changed, the measurement operation portion measuring the current flowing for each of plural measurement points of a surface of the semiconductor sample while causing the probe to scan the measurement points, or while sequentially bringing the probe into contact with the measurement points. A display displays a relationship between the voltage and the current measured at each of the measurement points.
    Type: Application
    Filed: August 27, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun HIROTA, Tsukasa NAKAI, Masako KOBAYASHI, Kazunori HARADA
  • Patent number: 10345336
    Abstract: A scanning probe microscope that includes a probe, a positioning unit configured to position a probe on a measurement sample, an excitation unit configured to excite the measurement sample at a predetermined frequency, a resonance unit configured to output a frequency modulation signal by converting a change of a capacitance of the measurement sample, a lock-in amplifier configured to output a differential capacitance signal obtained by extracting a predetermined frequency component and a harmonic component of the predetermined frequency of the demodulated signal, a conversion unit configured to output data indicative of a relationship between a voltage applied to the measurement sample and the capacitance, a detecting unit that detects a voltage value corresponding to a feature point of the relationship data, and a main measurement control unit that measures electrical characteristics of the measurement sample subjected to a DC bias voltage substantially equal to the feature point voltage.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Hirota, Tsukasa Nakai, Haruko Akutsu
  • Publication number: 20170269123
    Abstract: A scanning probe microscope that includes a probe, a positioning unit configured to position a probe on a measurement sample, an excitation unit configured to excite the measurement sample at a predetermined frequency, a resonance unit configured to output a frequency modulation signal by converting a change of a capacitance of the measurement sample, a lock-in amplifier configured to output a differential capacitance signal obtained by extracting a predetermined frequency component and a harmonic component of the predetermined frequency of the demodulated signal, a conversion unit configured to output data indicative of a relationship between a voltage applied to the measurement sample and the capacitance, a detecting unit that detects a voltage value corresponding to a feature point of the relationship data, and a main measurement control unit that measures electrical characteristics of the measurement sample subjected to a DC bias voltage substantially equal to the feature point voltage.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun HIROTA, Tsukasa NAKAI, Haruko AKUTSU
  • Patent number: 9570514
    Abstract: According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobuaki Yasutake
  • Patent number: 9536894
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Hiroki Tokuhira
  • Patent number: 9536616
    Abstract: A non-volatile memory device includes a first electrode layer, a second electrode layer adjacent to the first electrode layer, a third electrode layer adjacent to the second electrode layer, a fourth electrode layer adjacent to the third electrode layer, and a channel body extending through the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in a first direction. The device further includes a circuit electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, the fourth electrode layer, and the channel body. The circuit providing the second electrode layer with a first potential, the third electrode layer with a second potential higher than the first potential, the fourth electrode layer with a third potential between the first potential and the second potential and the channel body with a potential rising in the first direction.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobutoshi Aoki
  • Publication number: 20160377651
    Abstract: A measuring method of a scanning probe microscopy moves the probe from the first measuring point to the second measuring point while the probe has contact with the object to be measured and a pressing force weaker than the first pressing force is applied between the probe and the object to be measured after the measurement at the first measuring point has ended, applies the first pressing force between the probe and the object to be measured until the tip end position of the probe reaches the first distance in the depth direction from the upper surface of the object to be measured, and measures the physical property information of the object to be measured after the tip end position of the probe has reached the first distance in the depth direction from the upper surface of the object to be measured at the second measuring point.
    Type: Application
    Filed: March 11, 2016
    Publication date: December 29, 2016
    Inventors: Jun HIROTA, Kazunori Harada, Tsukasa Nakai
  • Publication number: 20160372206
    Abstract: A non-volatile memory device includes a first electrode layer, a second electrode layer adjacent to the first electrode layer, a third electrode layer adjacent to the second electrode layer, a fourth electrode layer adjacent to the third electrode layer, and a channel body extending through the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in a first direction. The device further includes a circuit electrically connected to the first electrode layer, the second electrode layer, the third electrode layer, the fourth electrode layer, and the channel body. The circuit providing the second electrode layer with a first potential, the third electrode layer with a second potential higher than the first potential, the fourth electrode layer with a third potential between the first potential and the second potential and the channel body with a potential rising in the first direction.
    Type: Application
    Filed: December 15, 2015
    Publication date: December 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobutoshi Aoki
  • Patent number: 9450026
    Abstract: According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobuaki Yasutake
  • Patent number: 9379164
    Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: June 28, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa Nakai, Masaki Kondo, Hikari Tajima, Hiroki Tokuhira, Takashi Izumida, Takashi Kurusu, Nobutoshi Aoki, Takahisa Kanemura, Tadayoshi Uechi
  • Patent number: 9287499
    Abstract: An integrated circuit device according to an embodiment includes an electrode extending in a first direction, two semiconductor members spaced from each other in the first direction and extending in a second direction crossing the first direction, an insulating film placed between each of the two semiconductor members and the electrode and made of a first insulating material, and a first dielectric member placed between the two semiconductor members and made of a second insulating material having a higher permittivity than the first insulating material.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobuaki Yasutake
  • Publication number: 20160064452
    Abstract: A memory device according to an embodiment includes a memory element; and a transistor including a semiconductor layer and a plurality of gates, wherein the plurality of gates include: a first set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, and a second set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, the gates included in the first set is disposed in a manner to separate from the gates included in the second set in a direction along a side surface of the semiconductor layer.
    Type: Application
    Filed: January 12, 2015
    Publication date: March 3, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshihiro UEDA, Tsukasa NAKAI, Masaki KONDO, Hikari TAJIMA, Hiroki TOKUHIRA, Takashi IZUMIDA
  • Publication number: 20160035741
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.
    Type: Application
    Filed: February 11, 2015
    Publication date: February 4, 2016
    Inventors: Hikari TAJIMA, Masaki KONDO, Tsukasa NAKAI, Takashi IZUMIDA, Hiroki TOKUHIRA
  • Publication number: 20150357379
    Abstract: According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hikari TAJIMA, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobuaki Yasutake
  • Publication number: 20150349252
    Abstract: An integrated circuit device according to an embodiment includes an electrode extending in a first direction, two semiconductor members spaced from each other in the first direction and extending in a second direction crossing the first direction, an insulating film placed between each of the two semiconductor members and the electrode and made of a first insulating material, and a first dielectric member placed between the two semiconductor members and made of a second insulating material having a higher permittivity than the first insulating material.
    Type: Application
    Filed: August 20, 2014
    Publication date: December 3, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hikari TAJIMA, Masaki KONDO, Tsukasa NAKAI, Takashi IZUMIDA, Nobuaki YASUTAKE
  • Publication number: 20150340605
    Abstract: An integrated circuit device according to an embodiment includes two electrodes and two semiconductor layers. The two electrodes extend in a first direction. The two semiconductor layers are placed between the two electrodes, are spaced from each other in the first direction, and extend in a second direction orthogonal to the first direction. The two electrodes include extending parts extending out so as to come close to each other. In a cross section orthogonal to the second direction, the extending parts extend into a region interposed between a pair of tangent lines. The pair of tangent lines tangent to both the two semiconductor layers and do not cross each other.
    Type: Application
    Filed: August 21, 2014
    Publication date: November 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hikari TAJIMA, Masaki KONDO, Tsukasa NAKAI, Takashi IZUMIDA, Nobuaki YASUTAKE
  • Publication number: 20150270312
    Abstract: According to an embodiment, a semiconductor device includes at least two control electrodes, a plurality of semiconductor layers and an insulating film. Each control electrode extends in a first direction. The semiconductor layers are provided between the control electrodes, and arranged in the first direction. Each semiconductor layer extends in a second direction orthogonal to the first direction. The insulating film covers side surfaces of the semiconductor layers, and is disposed between the control electrodes. Each semiconductor layer has a side surface that includes at least one curved surface swelling in a direction from a center of the semiconductor layer to the insulating film.
    Type: Application
    Filed: August 21, 2014
    Publication date: September 24, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hikari TAJIMA, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Nobuaki Yasutake
  • Patent number: 9142771
    Abstract: According to one embodiment, a memory device includes a stacked film stacked in a superlattice structure. The stacked film includes a first layer, a second layer, and a third layer different in composition. The first layer is provided between the second layer and the third layer. The second layer includes a first atom reversibly moved by application of energy. The third layer includes a second atom reversibly moved by application of energy. The second atom is different from the first atom.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Aoi Hidaka, Tsukasa Nakai