Patents by Inventor Tsukasa Ohishi

Tsukasa Ohishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LCD connected to additional LCD through multiple flexible printed circuit boards
    Patent number: 7233382
    Abstract: This invention is to provide a liquid crystal module that enables a liquid crystal display (LCD) device to be further miniaturized. The liquid crystal module is configured to include at least two LCD devices and formed separately from each other, a first flexible substrate on which a semiconductor chip for driving the LCD devices and is mounted, and a second flexible substrate wherein signal transmission wiring is formed. One of the LCD devices and is electrically connected to the first flexible substrate, the other one of the LCD devices and is electrically connected to the second flexible substrate, and the first flexible substrate is electrically connected to the second flexible substrate.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: June 19, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuhisa Yamaji, Yasunori Chikawa, Tsukasa Ohishi
  • Liquid crystal module
    Publication number: 20040189926
    Abstract: This invention is to provide a liquid crystal module that enables a liquid crystal display (LCD) device to be further miniaturized. The liquid crystal module is configured to include at least two LCD devices and formed separately from each other, a first flexible substrate on which a semiconductor chip for driving the LCD devices and is mounted, and a second flexible substrate wherein signal transmission wiring is formed. One of the LCD devices and is electrically connected to the first flexible substrate, the other one of the LCD devices and is electrically connected to the second flexible substrate, and the first flexible substrate is electrically connected to the second flexible substrate.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 30, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasuhisa Yamaji, Yasunori Chikawa, Tsukasa Ohishi
  • Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages
    Patent number: 5321657
    Abstract: In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: June 14, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazutami Arimoto, Kazuyasu Fujishima, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi
  • Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages
    Patent number: RE36027
    Abstract: In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
    Type: Grant
    Filed: June 13, 1996
    Date of Patent: January 5, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazutami Arimoto, Kazuyasu Fujishima, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi