Patents by Inventor Tsukasa Onodera

Tsukasa Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220166074
    Abstract: A power storage system includes a storage unit, a charging circuit configured to supply a charging current to the storage unit, and a controller connected to the storage unit. The storage unit includes plural capacitor elements connected in series to one another each having both ends, plural resistors connected to the capacitor elements, and plural switch elements connected to the capacitor elements and the resistors. One of both ends of each capacitor element of the plural capacitor elements is connected to one end of a corresponding resistor of the plural resistors. Another of the both ends of the each capacitor element is connected to one end of a corresponding switch element of the plural switch elements. Another end of the corresponding resistor is connected to another end of the corresponding switch element.
    Type: Application
    Filed: May 21, 2020
    Publication date: May 26, 2022
    Inventors: YOUICHI KAGEYAMA, TAKASHI HIGASHIDE, KATSUNORI ATAGO, KAZUO TAKENAKA, HISAO HIRAGI, YUGO SETSU, HIROKI NISHINAKA, TSUKASA ONODERA
  • Patent number: 4791471
    Abstract: In a semiconductor integrated circuit device, a plurality of a field effect transistors are formed on a (110) crystal surface of a group III-V compound semiconductor substrate having a zinc blend type crystal structure.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: December 13, 1988
    Assignee: Fujitsu Limited
    Inventors: Tsukasa Onodera, Haruo Kawata, Toshiro Futatsugi
  • Patent number: 4777517
    Abstract: An IC device comprising a plurality of FET's using a compound semiconductor, more specifically, a zincblende type semiconductor substrate, having a surface of a (111) plane. By use of this plane, differences of characteristics of the FET's depending on directions along which gates of the FET's are arranged when the gate length is made shorter are prevented, allowing arrangement of gates of the FET's in different directions, particularly perpendicular to each other, with making the gate length shorter to miniaturize and densify the device.
    Type: Grant
    Filed: November 26, 1985
    Date of Patent: October 11, 1988
    Assignee: Fujitsu Limited
    Inventors: Tsukasa Onodera, Haruo Kawata, Toshiro Futatsugi