Patents by Inventor Tsukasa Saiki
Tsukasa Saiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9515104Abstract: A semiconductor device includes a semiconductor substrate, a light receiving element region, a peripheral region, a boundary region, a plurality of signal lines, and a conductive layer. In light receiving element region, light receiving elements for performing photoelectric conversion are formed. Peripheral region is formed outside light receiving element region for performing input/output of an electric signal from/to the outside of the semiconductor substrate. Boundary region is formed between light receiving element region and peripheral region. The plurality of signal lines are arranged in boundary region for performing input/output of electric signals between light receiving element region and peripheral region. Conductive layer is arranged in a layer different from each of the plurality of signal lines. A relative position of conductive layer as seen from each of the plurality of signal lines is all identical, and conductive layer is all arranged in an identical layer.Type: GrantFiled: November 28, 2013Date of Patent: December 6, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tsukasa Saiki, Shido Tanaka
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Publication number: 20140151832Abstract: A semiconductor device includes a semiconductor substrate, a light receiving element region, a peripheral region, a boundary region, a plurality of signal lines, and a conductive layer. In light receiving element region, light receiving elements for performing photoelectric conversion are formed. Peripheral region is formed outside light receiving element region for performing input/output of an electric signal from/to the outside of the semiconductor substrate. Boundary region is formed between light receiving element region and peripheral region. The plurality of signal lines are arranged in boundary region for performing input/output of electric signals between light receiving element region and peripheral region. Conductive layer is arranged in a layer different from each of the plurality of signal lines. A relative position of conductive layer as seen from each of the plurality of signal lines is all identical, and conductive layer is all arranged in an identical layer.Type: ApplicationFiled: November 28, 2013Publication date: June 5, 2014Applicant: Renesas Electronics CorporationInventors: Tsukasa Saiki, Shido Tanaka
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Publication number: 20010040827Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRUM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: ApplicationFiled: January 10, 2000Publication date: November 15, 2001Inventors: KATSUMI DOSAKA, MASAKI KUMANOYA, YASUHIRO KONISHI, KATSUMITSU HIMUKASHI, KOUJI HAYANO, AKIRA YAMAZAKI, HISASHI IWAMOTO, HIDEAKI ABE, YASUHIRO ISHIZUKA, TSUKASA SAIKI
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Patent number: 6026029Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: May 29, 1997Date of Patent: February 15, 2000Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5848004Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: March 28, 1996Date of Patent: December 8, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5652723Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: April 15, 1992Date of Patent: July 29, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5650968Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: May 21, 1996Date of Patent: July 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5629895Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: April 30, 1996Date of Patent: May 13, 1997Assignees: Mitsubishi Electric Engineering Co., Ltd., Mitsubishi Denki Kabushiki KaishaInventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5623454Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: February 9, 1996Date of Patent: April 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5583813Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: December 10, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5559750Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: September 24, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: 5544121Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption.Type: GrantFiled: June 5, 1995Date of Patent: August 6, 1996Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.Inventors: Katsumi Dosaka, Masaki Kumanoya, Kouji Hayano, Akira Yamazaki, Hisashi Iwamoto, Hideaki Abe, Yasuhiro Konishi, Katsumitsu Himukashi, Yasuhiro Ishizuka, Tsukasa Saiki
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Patent number: D287117Type: GrantFiled: October 9, 1984Date of Patent: December 9, 1986Assignee: Hitachi, Ltd.Inventors: Tsukasa Saiki, Nobuyuki Kajima, Ryouichi Abe, Tatsuo Hujiwara