Patents by Inventor Tsukasa Shibuya

Tsukasa Shibuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6172671
    Abstract: There is provided an active matrix type display in which thin film transistors having required characteristics are provided selectively in a pixel matrix portion and a peripheral driving circuit portion. In a structure having the pixel matrix portion and the peripheral driving circuit portion on the same substrate, N-channel type thin film transistors having source and drain regions formed through a non-self-alignment process and low concentrate impurity regions formed through a self-alignment process are formed in the pixel matrix portion and in an N-channel driver portion of the peripheral driving circuit portion. A P-channel type thin film transistor in which no low concentrate impurity region is formed and source and drain regions are formed only through the self-alignment process is formed in a P-channel driver portion of the peripheral driving circuit portion.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: January 9, 2001
    Assignee: Semiconductor Energy Laboratory, Inc.
    Inventors: Tsukasa Shibuya, Atsushi Yoshinouchi, Hongyong Zhang, Akira Takenouchi
  • Patent number: 6078060
    Abstract: The invention provides a peripheral drive circuit integrated active matrix LCD device in which thin-film transistors have different characteristics optimized for individual circuits of the active matrix LCD device. A pixel matrix portion includes thin-film transistors, each having offset gate regions 134 and 136 produced in a non-self-alignment manner, an n-channel driver portion includes thin-film transistors, each having lightly-doped regions 128 and 130 produced in a combination of the non-self-alignment manner and a self-alignment manner, and a p-channel driver portion includes thin-film transistors produced in a self-alignment manner. This construction makes it possible to arrange the thin-film transistors having characteristics required by the individual circuits.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: June 20, 2000
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Tsukasa Shibuya, Atsushi Yoshinouchi, Hongyong Zhang, Nobuo Kubo
  • Patent number: 6013544
    Abstract: A method for fabricating a semiconductor device including an active region obtained by utilizing a silicon semiconductor film having crystallinity which is formed on an insulating substrate is disclosed. A crystalline silicon semiconductor film is obtained by introducing catalyst elements for promoting the crystallization into a lower amorphous silicon semiconductor film and then performing a heat treatment onto the lower amorphous silicon semiconductor film. Thereafter, an upper amorphous silicon semiconductor film is formed on the obtained lower crystalline silicon semiconductor film, which is subsequently subjected to a heat treatment so as to obtain an upper crystalline silicon semiconductor film. Then, the upper crystalline silicon semiconductor film is removed. By this process, the catalyst elements remaining in the lower crystalline silicon semiconductor film moves into the upper crystalline silicon semiconductor film.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: January 11, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Tadayoshi Miyamoto, Tsukasa Shibuya
  • Patent number: 5923961
    Abstract: There is provided an active matrix type display in which thin film transistors having required characteristics are provided selectively in a pixel matrix portion and a peripheral driving circuit portion. In a structure having the pixel matrix portion and the peripheral driving circuit portion on the same substrate, N-channel type thin film transistors having source and drain regions formed through a non-self-alignment process and low concentrate impurity regions formed through a self-alignment process are formed in the pixel matrix portion and in an N-channel driver portion of the peripheral driving circuit portion. A P-channel type thin film transistor in which no low concentrate impurity region is formed and source and drain regions are formed only through the self-alignment process is formed in a P-channel driver portion of the peripheral driving circuit portion.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: July 13, 1999
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Tsukasa Shibuya, Atsushi Yoshinouchi, Hongyong Zhang, Akira Takenouchi
  • Patent number: 5818068
    Abstract: A TFT circuit according to the present invention includes a first transistor and a second transistor both formed on an insulating substrate. The first transistor has a channel region comprising a polycrystalline silicon film to which a metal element for enhancing crystallization is added. The second transistor has a channel region comprising a polycrystalline silicon film to which no metal element for enhancing crystallization is added.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: October 6, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Osamu Sasaki, Manabu Matsuura, Tsukasa Shibuya, Yasushi Kubota
  • Patent number: 5814835
    Abstract: The semiconductor device of invention includes: a substrate having an insulating surface; and an element region formed by crystallizing an amorphous silicon film, the element region being provided on the insulating surface of the substrate. In the semiconductor device, the element region is constituted by a laterally crystallized region formed by crystallizing the amorphous silicon film from a linearly crystallized region crystallized by a selective introduction of catalyst elements for promoting a crystallization of the amorphous silicon film to a region surrounding the linearly crystallized region by performing a heat-treatment, and a concentration of the catalyst elements in at least one of the laterally crystallized region and the linearly crystallized region is controlled by a line width of an introduction setting region having a linear planar pattern, the line width being set so as to selectively introduce the catalyst elements.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: September 29, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Tadayoshi Miyamoto, Tsukasa Shibuya, Masashi Maekawa
  • Patent number: 5624861
    Abstract: A manufacturing method of a semiconductor device includes the steps of depositing a metallic film (light-shielding film), an insulating film and a semiconductor film in this order on an insulating substrate, and after patterning the insulating film and the semiconductor film in a predetermined shape, oxidizing an exposed region of the metallic film using the insulating film and the semiconductor film as a mask. As a result, the light-shielding film composed of the metallic film is formed so as to cover the semiconductor film to block light from an external portion. The manufacturing method permits a process of forming a resist pattern for use in forming the light-shielding film and a process of etching the light-shielding film to be omitted, thereby reducing the required number of processes. Moreover, as a level difference is not generated around the light-shielding film, a generation of a level difference on the semiconductor film can be prevented.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: April 29, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tsukasa Shibuya