Patents by Inventor Tsukio Funaki

Tsukio Funaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7176569
    Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: February 13, 2007
    Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.
    Inventor: Tsukio Funaki
  • Publication number: 20070023924
    Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate.
    Type: Application
    Filed: September 7, 2006
    Publication date: February 1, 2007
    Inventor: Tsukio Funaki
  • Patent number: 6787395
    Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 7, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida
  • Publication number: 20040159958
    Abstract: Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 19, 2004
    Applicants: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.
    Inventor: Tsukio Funaki
  • Publication number: 20030032218
    Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.
    Type: Application
    Filed: October 15, 2002
    Publication date: February 13, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida
  • Patent number: 6489181
    Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: December 3, 2002
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida
  • Publication number: 20020013015
    Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 31, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida