Patents by Inventor Tsukui Seiichiro

Tsukui Seiichiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory module having double-sided stacked memory chip layout
    Patent number: 6693346
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: February 17, 2004
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided stacked memory chip layout
    Publication number: 20030098504
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Application
    Filed: January 14, 2003
    Publication date: May 29, 2003
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided stacked memory chip layout
    Patent number: 6521993
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: February 18, 2003
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided stacked memory chip layout
    Publication number: 20020121690
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Application
    Filed: April 18, 2002
    Publication date: September 5, 2002
    Applicant: Hitachi, Ltd. (JP)
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided stacked memory chip layout
    Patent number: 6424030
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: July 23, 2002
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided stacked memory chip layout
    Publication number: 20010020741
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Application
    Filed: May 24, 2001
    Publication date: September 13, 2001
    Applicant: Hitachi Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided memory chip layout
    Patent number: 6262488
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: July 17, 2001
    Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.,
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Semiconductor memory module having double-sided stacked memory chip layout
    Patent number: 5708298
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: January 13, 1998
    Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Process for manufacturing a stacked integrated circuit package
    Patent number: 5587341
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: December 24, 1996
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Lead connections means for stacked tab packaged IC chips
    Patent number: 5138438
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: August 11, 1992
    Assignees: Akita Electronics Co. Ltd., Hitachi Ltd., Hitachi Semiconductor Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki