Patents by Inventor Tsun Ho Liu
Tsun Ho Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119993Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Kathik Gopalakrishnan, Tsun Ho Liu
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Patent number: 11947833Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.Type: GrantFiled: June 21, 2022Date of Patent: April 2, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Tsun Ho Liu
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Patent number: 11854602Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.Type: GrantFiled: June 27, 2022Date of Patent: December 26, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Publication number: 20230409232Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani, Tsun Ho Liu
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Publication number: 20230178138Abstract: A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.Type: ApplicationFiled: June 27, 2022Publication date: June 8, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Publication number: 20230176786Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.Type: ApplicationFiled: June 27, 2022Publication date: June 8, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Publication number: 20230176608Abstract: A memory includes a read clock state machine and a read clock driver circuit. The read clock state machine has a first input for receiving a read command signal, a second input for receiving a read clock mode signal, and an output for providing a drive enable signal. The read clock driver circuit has an output for providing a read clock signal in response to a clock signal when the drive enable signal is active. When the read clock mode signal indicates a read-only mode, the read clock state machine starts toggling the read clock signal during a read preamble period before a data transmission of a first read command, and continues toggling the read clock signal for at least a read postamble period following the data transmission of the first read command.Type: ApplicationFiled: June 27, 2022Publication date: June 8, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Publication number: 20230178126Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.Type: ApplicationFiled: June 30, 2022Publication date: June 8, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron John Nygren, Michael John Litt, Karthik Gopalakrishnan, Tsun Ho Liu
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Patent number: 10853216Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.Type: GrantFiled: June 15, 2015Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Tsun Ho Liu, Andre Schaefer, Hoi M. Ng, Guy R. Murray, Oleg Mikulchenko, Xiaofang Gao
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Publication number: 20150317228Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.Type: ApplicationFiled: June 15, 2015Publication date: November 5, 2015Applicant: INTEL CORPORATIONInventors: Tsun Ho LIU, Andre Schaefer, Hoi M. Ng, Guy R. Murray, Oleg Mikulchenko, Xiaofang Gao
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Patent number: 9086881Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.Type: GrantFiled: June 29, 2012Date of Patent: July 21, 2015Assignee: Intel CorporationInventors: Tsun Ho Liu, Andre Schaefer, Hoi M. Ng, Guy R. Murray, Oleg Mikulchenko, Xiaofang Gao
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Publication number: 20140089755Abstract: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Inventors: Shveta KANTAMSETTI, Antonio JUAN, Hoi M. NG, Warren R. MORROW, Isaac HERNANDEZ, Pau CABRE, Thomas S. NG, Tsun Ho LIU, Rongchun SUN, Jessica LEUNG, Mohamedsha MALIKANSARI, Henry STRACOVSKY
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Publication number: 20140006702Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Tsun Ho Liu, Andre Schaefer, Hoi M. Ng, Guy R. Murray, Oleg Mikulchenko, Xiaofang Gao