Patents by Inventor Tsun Kai Tsao

Tsun Kai Tsao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12317613
    Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Wei Chuang Wu
  • Publication number: 20250031472
    Abstract: Embodiments of the present disclosure relate to a structure, which includes a plurality of photodiode doping regions formed in a substrate, and a deep trench isolation (DTI) structure formed in the substrate, wherein the DTI structure separates photodiode doping regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material includes a top, a sidewall, and a bottom. The structure also includes a first isolation layer surrounding and in contact with the top, the sidewall, and the bottom of the first filling material.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Sheng Chieh CHUANG, Shu Yen KUNG, Tsun-Kai TSAO, Ming Chyi LIU
  • Publication number: 20240332163
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Che Wei YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Publication number: 20240290806
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a mask layer on a first side of a semiconductor substrate. The mask layer comprises a plurality of sidewalls defining a plurality of openings. A first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. A second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.
    Type: Application
    Filed: April 30, 2024
    Publication date: August 29, 2024
    Inventors: Tsun-Kai Tsao, Cheng-Hsien Chou, Jiech-Fun Lu
  • Patent number: 12046550
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Paul Yang, Tsun-Kai Tsao, Sheng-Chau Chen, Sheng-Chan Li, Cheng-Yuan Tsai
  • Patent number: 12027554
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 12002828
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Cheng-Hsien Chou, Jiech-Fun Lu
  • Publication number: 20240088187
    Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 14, 2024
    Inventors: Chih Cheng Shih, Tsun-Kai Tsao, Jiech-Fun Lu, Hung-Wen Hsu, Bing Cheng You, Wen-Chang Kuo
  • Publication number: 20240021653
    Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Wei Chuang Wu
  • Publication number: 20230387163
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an optical device within or on a semiconductor substrate. A light guide structure overlies the optical device. A first etch stop layer extends along first sidewalls and a lower surface of the light guide structure. A second etch stop layer overlies the first etch stop layer and extends along second sidewalls of the light guide structure.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Tzu-Ming Wang
  • Publication number: 20230369368
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a lower reflectivity than the first material.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11812608
    Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsun-Kai Tsao, Hung-Ling Shih, Po-Wei Liu, Shun-Shing Yang, Wen-Tuo Huang, Yong-Shiuan Tsair, ShihKuang Yang
  • Patent number: 11776985
    Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Wei Chuang Wu
  • Patent number: 11769778
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor. The method includes forming a photodetector in a substrate. A lower interconnect portion of an interconnect structure is formed over the photodetector. A removal process is performed to define a first opening overlying the photodetector in the lower interconnect portion. A lower etch stop layer is formed lining the first opening. The lower etch stop layer has a U-shape in the first opening. An upper interconnect portion of the interconnect structure is formed over the lower etch stop layer. A light pipe structure is formed overlying the photodetector. The U-shape of the lower etch stop layer extends continuously along sidewalls and a bottom surface of the light pipe structure.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Jiech-Fun Lu, Shih-Pei Chou, Tzu-Ming Wang
  • Publication number: 20230299106
    Abstract: A method includes: forming a masking layer on a backside of a substrate, the substrate including pixel regions having photodetectors, transistors being positioned on or in a frontside of the substrate; forming a mask opening in the masking layer by exposing the masking layer to patterned light, the opening including: mask pixel regions that mask the pixel regions; and mask protrusion regions that extend from the mask pixel regions toward a mask crossroad region; forming a substrate opening in the substrate by etching the substrate through the mask opening; and forming an isolation structure in the substrate opening.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 21, 2023
    Inventors: Shu Yen Kung, Jia-Hong Liou, Sheng Chieh Chuang, Chun-Chang Chen, Wei-Lin Chang, Ming Chyi Liu, Tsun-Kai Tsao
  • Publication number: 20230207448
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 29, 2023
    Inventors: Paul YANG, Tsun-Kai TSAO, Sheng-Chau CHEN, Sheng-Chan LI, Cheng-Yuan TSAI
  • Patent number: 11600647
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Cheng-Hsien Chou, Jiech-Fun Lu
  • Patent number: 11581254
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Paul Yang, Tsun-Kai Tsao, Sheng-Chau Chen, Sheng-Chan Li, Cheng-Yuan Tsai
  • Publication number: 20220367559
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Yung-Lung Yang
  • Patent number: 11502123
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang