Patents by Inventor TSUN-MING WANG

TSUN-MING WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363344
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Patent number: 12062541
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Chiao-Tung University
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Publication number: 20220367176
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Patent number: 11437235
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Chiao-Tung University
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Publication number: 20210057211
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Patent number: 10854446
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 1, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Chiao-Tung University
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Publication number: 20190006173
    Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
    Type: Application
    Filed: August 13, 2018
    Publication date: January 3, 2019
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Patent number: 10049872
    Abstract: A method includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Chiao-Tung University
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Publication number: 20160189952
    Abstract: A method includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: HUNG-WEI YU, YI CHANG, TSUN-MING WANG
  • Patent number: 9287122
    Abstract: Disclosed is a method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication process. The method comprises providing a prelayer over a substrate, providing a barrier layer over the prelayer, and providing an InAs or Sb-based channel layer over the barrier layer. The substrate comprises a gallium arsenide substrate, a silicon substrate, a germanium substrate, or a Ge/Si substrate. The prelayer comprises a graded-temperature arsenic prelayer grown with graded temperature ramped from 300 to 550° C. The barrier layer comprises GaAs with low-growth-temperature growth or an InxGa1-xAs epitaxy with one or multiple GaAs-based layers. The channel layer comprises an InAs epitaxy with low-growth-temperature growth or Al(In)Sb/InAs/Al(In)Sb heterostructures with one or more pairs.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Wei Yu, Yi Chang, Tsun-Ming Wang
  • Publication number: 20150262810
    Abstract: Disclosed is a method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication process. The method comprises providing a prelayer over a substrate, providing a barrier layer over the prelayer, and providing an InAs or Sb-based channel layer over the barrier layer. The substrate comprises a gallium arsenide substrate, a silicon substrate, a germanium substrate, or a Ge/Si substrate. The prelayer comprises a graded-temperature arsenic prelayer grown with graded temperature ramped from 300 to 550° C. The barrier layer comprises GaAs with low-growth-temperature growth or an InxGa1-xAs epitaxy with one or multiple GaAs-based layers. The channel layer comprises an InAs epitaxy with low-growth-temperature growth or Al(In)Sb/InAs/Al(In)Sb heterostructures with one or more pairs.
    Type: Application
    Filed: August 6, 2014
    Publication date: September 17, 2015
    Inventors: HUNG-WEI YU, YI CHANG, TSUN-MING WANG