Abstract: A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.

Abstract: Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.

Abstract: In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

Abstract: A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

Abstract: A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cycle of the external clock signal. A logic circuit 8 generates an internal clock signal which rises in synchronism with the external clock signal and falls in synchronism with the pulse signal thus delayed. Hence, the internal clock signal has the same cycle as the external clock signal and has a desired duty ratio of (1/2.sup.K).times.100%.

Abstract: The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.

Abstract: A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.

Abstract: A level shift element is contained in a through current path of a CMOS gate of a BiCMOS circuit. The level shift element limits an amplitude of an input signal to the BiCMOS circuit. The limited amplitude of the input signal controls the impact ionization within the CMOS gate, and the increase of a substrate current resulting from the impact ionization, and reduces the through current.

Abstract: A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage V.sub.CE is controlled according to the base potential to satisfy the condition of I.sub.BE <I.sub.CB when the forward base current in the base-emitter path and the reverse base current in the collector-base path are respectively expressed by I.sub.BE and I.sub.CB and a switching element connected to the bipolar transistor, word lines, bit lines and emitter electrode lines connected to the memory cells, and functions as a dynamic memory cell in the data storing operation and as a gain memory cell in the readout operation.

Abstract: Bit-line pairs and word lines are disposed perpendicular to one another and dRAM cells are placed at their intersections. A dummy cell is connected to each of the bit-line pairs. A bit-line sense amplifier and an equalizer are connected to one end of the bit-line pair. The other end of the bit-line pair is connected to a latch type memory cell via a first transfer gate. The latch type memory cell are further connected to input/output line pair via a second transfer gate controlled by a column select line. During a RAS active period in a read cycle a word line is selected so that data is read from a dRAM cell and the dummy cell connected to the selected word line onto the bit-line pairs. The bit-line sense amplifiers are activated so that the levels of the bit lines become determinate. The first transfer gates are subsequently turned on to transfer the data on the bit-line pairs to the latch type cells.

Abstract: A dynamic random access semiconductor memory device includes a bit line pair to which at least one memory cell is connected, a bit line sense amplifier connected between the bit line pair and an input/output line pair, and a word line connected to the memory cell. The bit line sense amplifier includes a differential amplifier whose driving transistors are bipolar transistors. The bit line pair is selected at a first timing by a row address signal and the word line is selected at a second timing following the first timing by a column address signal.