Patents by Inventor Tsuneaki Hikita

Tsuneaki Hikita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7315058
    Abstract: To prevent the extraction of electrons from the floating gate during a read operation. A semiconductor memory device comprises a selection gate 3a provided in a first region on a substrate 1 through an insulating film 2, a floating gate 6a provided in a second region adjacent to the first region through an insulating film 5, a first and second diffusion regions 7a and 7b provided in a third region adjacent to the second region, and a control gate 11 provided over the floating gate 6a through an insulating film 8, the control gate 11 intersects with the selection gate 3a at different levels, a third diffusion region 21 is provided in a fourth region located near an extending part of the selection gate 3a on the surface of the substrate, the floating gate 6a is formed in the form of a side wall, and it has a round part 6b at the top on the side directed to the side wall surface of the selection gate 3a.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: January 1, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Tsuneaki Hikita
  • Publication number: 20070052006
    Abstract: To prevent the extraction of electrons from the floating gate during a read operation. A semiconductor memory device comprises a selection gate 3a provided in a first region on a substrate 1 through an insulating film 2, a floating gate 6a provided in a second region adjacent to the first region through an insulating film 5, a first and second diffusion regions 7a and 7b provided in a third region adjacent to the second region, and a control gate 11 provided over the floating gate 6a through an insulating film 8, the control gate 11 intersects with the selection gate 3a at different levels, a third diffusion region 21 is provided in a fourth region located near an extending part of the selection gate 3a on the surface of the substrate, the floating gate 6a is formed in the form of a side wall, and it has a round part 6b at the top on the side directed to the side wall surface of the selection gate 3a.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tsuneaki Hikita