Patents by Inventor Tsuneaki Kamei

Tsuneaki Kamei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5942185
    Abstract: Provided is a lead-free solder for connecting LSI and parts on organic substrates, which can provide soldering at a maximum temperature of 220.degree.-230.degree. C. and which has a sufficient reliability in mechanical strength even at a high temperature of 150.degree. C. Also provided are electronic products prepared using this lead-free solder. The lead-free solder has a solder composition including 3-5% Zn and 10-23% Bi, the balance being Sn. Preferably, the solder composition is a composition (Sn, Zn, Bi) surrounded by lines connecting A and B, B and C and C and A, where A is (85, 5, 10 ), B is (72, 5, 23) and C is (76, 3, 21), of a ternary diagram having pure Sn, pure Zn and pure Bi at the vertices of an equilateral triangle. Through use of this solder, it is possible to solder parts, etc. on conventionally employed organic substrates at reflow temperatures equivalent to those for conventional Pb--Sn eutectic solders. The solder does not damage the environment, can be stably supplied and is low in cost.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: August 24, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Tasao Soga, Hanae Shimokawa, Kenichi Yamamoto, Masahide Harada, Yuuji Ochiai, Tsuneaki Kamei
  • Patent number: 5867809
    Abstract: The present invention relates to an electric appliance and a remaining life estimation system wherein the electric appliance having a printed circuit board on which at least LSI components are mounted includes an IC with sensor. The IC includes a time monitor for calculating the operation status which is a use condition affecting the life of a reusable component of the appliance, a temperature and humidity sensor for detecting at least temperature and humidity environmental conditions affecting the life of the reusable component, and a memory for storing the history of temperature and humidity in correspondence with the history of operation status.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: February 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tasao Soga, Hanae Shimokawa, Masahide Harada, Tatsuya Suzuki, Yuji Ochiai, Asao Nakano, Hiroyoshi Matsumura, Tsuneaki Kamei
  • Patent number: 4963239
    Abstract: A sputtering process of a substrate biasing system and an apparatus for carrying out the same, capable of forming a film in satisfactory surface coverage over stepped underlying layer. The present invention solves problems in the quality of films formed by the conventional sputtering process of a substrate biasing system by regulating the bias potential of a substrate on which a film is to be formed so that the kinetic energy of ions of a sputtering gas falling on the substrate is varied periodically. The bias potential is regulated by periodically varying the amplitude of the output of a radio frequency (or dc) bias power supply or by changing the duty factor of a voltage pulse stream of the output of the radio frequency (or dc) bias power supply.
    Type: Grant
    Filed: January 26, 1989
    Date of Patent: October 16, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Shimamura, Masao Sakata, Shigeru Kobayashi, Yuji Yoneoka, Tsuneaki Kamei, Tsuneyoshi Kawahito, Shoyo Fujita, Hiroshi Nakamura
  • Patent number: 4806725
    Abstract: A circuit substrate, such as a thermal printing head, having electrodes made of a material suitable for soldering. The electrode to be soldered, at least in part, is composed of an alloy of Ni and Cu, whose composition ranges from 65 mol % Ni - 35 mol % Cu to 75 mol % Ni - 25 mol % Cu.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: February 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yasunori Narizuka, Keiji Mori, Akira Yabushita, Tsuneaki Kamei, Mamoru Morita
  • Patent number: 4724060
    Abstract: A target for use in a sputtering technique usually has a flat structure. The present invention has succeeded in endowing sputtering film formation with a directivity in such a way that the surface of the target is provided with recesses thereby to limit the flight directions of sputtering particles.Alternatively, the directivity can be bestowed by disposing a frame between a substrate to be formed with a film and the flat sputtering target. This measure requires auxiliary means in which a wall is provided at the outer periphery of the sputtering target so as to effectively utilize a plasma.The present invention actually formed films by the use of the above technique, and has verified the effect thereof. Wide applications are expected in technical fields wherein after forming a microscopic pattern, one or more films need to be further formed.
    Type: Grant
    Filed: November 14, 1985
    Date of Patent: February 9, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masao Sakata, Hideaki Shimamura, Shigeru Kobayashi, Tsuneyoshi Kawahito, Tsuneaki Kamei, Katsuo Abe
  • Patent number: 4610770
    Abstract: A pair of magnets for producing a mirror magnetic field are disposed outside of an electrode structure carrying a target. Microwaves from a microwave source are introduced toward and into a space defined by the mirror magnetic field for generating high-density plasma. While maintaining this high-density plasma over a wide area of the surface of the target, an electric field substantially perpendicular to the surface of the target is applied for sputtering of the target material. The optimized conditions for plasma generation can be selected when the high-density plasma formed outside of a processing chamber is guided to migrate toward an area above the target in the processing chamber. Capability of sputtering of the material from the entire surface of the target increases the rate of film deposition on a substrate and improves the target utilization rate (the quantity of the material deposited on the substrate/the usable area of the target).
    Type: Grant
    Filed: December 24, 1984
    Date of Patent: September 9, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Saito, Hideki Tateishi, Shigeru Kobayashi, Susumu Aiuchi, Yasumichi Suzuki, Masao Sakata, Hideaki Shimamura, Tsuneaki Kamei
  • Patent number: 4610774
    Abstract: A sputtering target structure suitable for use with a planar magnetron sputtering electrode device has a plurality of annular target members arranged concentrically. The annular target member is provided with either an annular groove for concentration of an electric field or an annular wall for repelling electrons.
    Type: Grant
    Filed: November 14, 1985
    Date of Patent: September 9, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Masao Sakata, Shigeru Kobayashi, Katsuo Abe, Hideaki Shimamura, Tsuneaki Kamei, Osamu Kasahara, Hidetsugu Ogishi, Takeshi Oyamada
  • Patent number: 4517444
    Abstract: Disclosed is a thermal printhead made of an insulating substrate, and a heat generating resistor layer formed on the substrate, and wherein the heat generating resistor layer is supplied with electric current. The heat generating resistor layer is made of Cr-Si-SiO alloy, and with the Cr, Si and SiO contents falling within a region defined by points A, B, C and D in a triangular diagram, where the points A, B, C and D are determined as follows:______________________________________ Cr (mol %) (Si (mol %) SiO (mol %) ______________________________________ A 79.4 2.1 18.5 B 58.6 40.9 0.5 C 10.1 89.4 0.5 D 24.4 3.7 71.9.
    Type: Grant
    Filed: January 20, 1984
    Date of Patent: May 14, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Tsuneyoshi Kawahito, Katsuo Abe, Tsuneaki Kamei, Kazuyuki Fujimoto, Masao Mitani, Shigetoshi Hiratsuka
  • Patent number: 4460494
    Abstract: Disclosed is a resistor made of an alloy consisting essentially of Cr, Si and SiO.
    Type: Grant
    Filed: November 9, 1982
    Date of Patent: July 17, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Katsuo Abe, Tsuneyoshi Kawahito, Tsuneaki Kamei, Masao Mitani, Kazuyuki Fujimoto, Shigetoshi Hiratsuka
  • Patent number: 4444635
    Abstract: A film forming method by plasma sputtering is provided to attain a composite film on a substrate. A target plate having metal materials in a different pattern is prepared in opposition to the substrate. A plasma is created by a planar magnetron sputtering electrode structure. The plasma is shifted magnetically on the target plate by at least three magnetically coupled magnetic poles to deposit the materials into a film with a uniform thickness and a desired composition on the substrate.
    Type: Grant
    Filed: July 21, 1982
    Date of Patent: April 24, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Shigeru Kobayashi, Nobuo Nakagawa, Katsuo Abe, Tsuneaki Kamei, Kazuyuki Fujimoto
  • Patent number: 4405435
    Abstract: An apparatus for performing continuous treatment in vacuum including an inlet chamber, a first intermediate chamber, at least one vacuum treating chamber, a second intermediate chamber and a withdrawing chamber arranged in the indicated order in a direction in which base plates are successively transferred. An opening device normally closed and opened when a base plate is transferred therethrough is mounted on a wall at the inlet of the inlet chamber, between the adjacent chambers and on a wall at the outlet side of the withdrawing chamber. A conveyor device for conveying each base plate in a horizontal direction through the opening device is mounted in each of the chambers, and an evacuating device is also mounted in each chamber. A base plate storing device for storing a plurality of base plates in a magazine is mounted in the first and second intermediate chambers. At least one vacuum treating device is mounted in the vacuum treating chamber.
    Type: Grant
    Filed: August 26, 1981
    Date of Patent: September 20, 1983
    Assignees: Hitachi, Ltd., Anelva Corporation
    Inventors: Hideki Tateishi, Tsuneaki Kamei, Katsuo Abe, Shigeru Kobayashi, Susumu Aiuchi, Masashi Nakatsukasa, Nobuyuki Takahashi, Ryuji Sugimoto
  • Patent number: 4401539
    Abstract: A sputtering apparatus of the planar magnetron type is disclosed, in which a low-pressure gas is ionized by glow discharge, ions in the plasma are accelerated by a voltage applied between a cathode and an anode to bombard a target structure, atoms or particles of a target material sputtered from the planar target plate by the bombardment of ions are deposited on a substrate disposed on the anode side, and thus a thin film made of the same material as the target material is formed on the substrate.
    Type: Grant
    Filed: January 29, 1982
    Date of Patent: August 30, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Katsuo Abe, Shigeru Kobayashi, Tsuneaki Kamei, Hideki Tateishi, Susumu Aiuchi
  • Patent number: 4343986
    Abstract: A thermal printhead comprising a substrate, heat generating thin film resistor bodies formed on the substrate and electric conductors for supplying the heat generating thin film resistor bodies with electric power, characterized in that the heat generating thin film resistor bodies are made of a Cr-Si alloy subjected to a stabilization aging heat treatment.
    Type: Grant
    Filed: March 19, 1981
    Date of Patent: August 10, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Masao Mitani, Toyoji Tsunoda, Tsuneyoshi Kawahito, Tsuneaki Kamei, Akira Yabushita
  • Patent number: 4161431
    Abstract: A thin film resistor is produced by forming a film of tantalum pentoxide on part of a pattern of tantalum nitride, simultaneously forming an electroconductor and an electrode on other part, where no film of tantalum pentoxide is formed, by means of a metal cheaper than gold, and heating the pattern in an inert gas atmosphere.
    Type: Grant
    Filed: December 14, 1977
    Date of Patent: July 17, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Takehiko Matsunaga, Saburo Umeda, Tsuneaki Kamei
  • Patent number: 4042726
    Abstract: A method for manufacturing a semiconductor device wherein semiconductor material is selectively removed from a principal surface of a semiconductor substrate having at least one semiconductor layer formed thereon to provide a groove that extends through said layer and into the substrate and wherein the semiconductor material of the substrate is selectively oxidized to form an oxide insulator layer within the groove. The groove has a width which is smaller than the thickness of the semiconductor layer and the oxide insulator layer serves to isolate a portion of the semiconductor layer from adjacent portions of the substrate.
    Type: Grant
    Filed: September 8, 1975
    Date of Patent: August 16, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tadao Kaji, Tsuneaki Kamei, Keiji Miyamoto
  • Patent number: 3997378
    Abstract: In the manufacture of a semiconductor device, when an epitaxially-grown layer is formed on a semiconductor substrate partially formed with an oxide, a polycrystalline layer is formed on the oxide; the polycrystalline part is used as an isolation region for elements to be formed in the epitaxially-grown layer. The oxide for growing the polycrystalline layer is buried and formed in the semiconductor substrate at a depth at which a breakdown voltage between the elements is attained, whereby the width of the isolation region can be made small, so as to increase the density of integration of the semiconductor device.
    Type: Grant
    Filed: October 17, 1975
    Date of Patent: December 14, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Tadao Kaji, Tsuneaki Kamei, Keiji Miyamoto