Patents by Inventor Tsuneaki Kudo

Tsuneaki Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Standard cells with flip-flops located in a single region and having minimal-length clock lines
    Patent number: 5029279
    Abstract: Standard cells in which the accurate estimation of the clock routing length and the minimization of the clock routing are possible so that an optimal protection against the malfunctions due to the racing can be schemed. The standard cells includes flip-flop circuits collectively arranged in a region of the substrate; and clock routing for the flip-flop circuits with connections connecting the clock routing and each of the flip-flop circuits at shortest distance.
    Type: Grant
    Filed: July 17, 1989
    Date of Patent: July 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tohru Sasaki, Takeji Tokumaru, Tsuneaki Kudo