Abstract: A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the input data, where each of the first signal and the second signal functions as a differential signal, a correction circuit generating a correction signal for correcting variation in current drive capabilities of two transistors of a first buffer included in at least one of the first circuit and the second circuit, and a second buffer coupled in parallel with the first buffer and reducing, based on the correction signal, the variation in the current drive capabilities of the two transistors.

Abstract: A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the input data, where each of the first signal and the second signal functions as a differential signal, a correction circuit generating a correction signal for correcting variation in current drive capabilities of two transistors of a first buffer included in at least one of the first circuit and the second circuit, and a second buffer coupled in parallel with the first buffer and reducing, based on the correction signal, the variation in the current drive capabilities of the two transistors.

Abstract: A differential amplifier of the present invention comprises transistors where to each of which one of two inputs to said differential amplifier is provided; current mirror circuits where each of which delivers one of the outputs of the differential amplifier to the load side; and cut-off prevention units where each of which is connected to the connecting point of a transistor to which a monitor current of one of the current mirror circuits flows, and one of the transistors to which the inputs are provided, and applies a current for preventing cutting off the transistor to which the monitor current flows, when the input to the transistor to which the input is provided is L.

Abstract: A differential amplifier of the present invention comprises transistors where to each of which one of two inputs to said differential amplifier is provided; current mirror circuits where each of which delivers one of the outputs of the differential amplifier to the load side; and cut-off prevention units where each of which is connected to the connecting point of a transistor to which a monitor current of one of the current mirror circuits flows, and one of the transistors to which the inputs are provided, and applies a current for preventing cutting off the transistor to which the monitor current flows, when the input to the transistor to which the input is provided is L.

Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Abstract: The differential amplifier of the present invention has a current source connected between a grounding wire and a terminal which can be the output point of the differential amplifier among the terminals of each transistor which constitutes the differential amplifier and to which one of two inputs to the differential amplifier is given, or a circuit element connected between the terminals which can be the output points of the differential amplifier, or two transistors which are connected to each of the terminals which can be the output points of the differential amplifier and one of which turns off when the other is on, and one of which turns on when the other is off, and the current source is connected between the two transistors and the grounding wire.

Abstract: A semiconductor circuit includes a decision feedback equalizer (DFE) for waveform-equalizing an input signal and generating a waveform-equalized input signal. The DFE compares the waveform-equalized signal with a predetermined reference voltage to generate a decision signal having first and second decision values and an error signal which lies between the waveform-equalized signal and the decision signal. A dispersion value calculator is connected to the DFE, calculates first and second dispersion values of the first and second decision values of the decision signal using the error signal, and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected to the DFE and the dispersion value calculator. The asymmetry compensator receives the input signal and corrects an asymmetry in the input signal in accordance with the compensation signal and supplies the corrected input signal to the DFE.

Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Abstract: A read channel for a hard disk includes a decision feedback equalizer (DFE) that is used to demodulate and decode a read signal from a read head or a received signal from a fast communication apparatus by eliminating intersymbol interference from sampled data of the read signal. The DFE has a feed forward equalizer (FFE) that filters the sampled data and generates filtered data. An adder is connected to the FFE and adds the filtered data with a feedback signal to generate an equalization signal. A decision unit connected to the adder compares the equalization signal with a reference signal and generates a decision signal. A shift register connected to the decision unit receives the decision signal. A feedback filter connected to the shift register and the adder receives the decision signal from the shift register and generates the feedback signal. The phase and frequency of a clock signal and the phase and frequency of the input signal are matched using the equalization signal and the decision signal.

Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Abstract: Disclosed is an apparatus for correcting error data contained in data read from an optical disk. The data correcting apparatus has a memory for storing data read out from the optical disk. The apparatus also has a syndrome generator for generating error syndrome data, and a circuit for detecting the position and value of data errors. The data correcting apparatus further includes a circuit for correcting errors in the read data stored in the memory, based on the error position and error value. The syndrome generator transfers a first ID data field for data identification together with the syndrome data via a first direct bus, provided between the syndrome generator and the detecting circuit. The detecting circuit transfers a second ID data field for data identification together with error information data via a second direct bus, provided between the detecting circuit and the data correcting circuit.