Abstract: To provide a radio frequency power amplifier that realizes a favorable high-frequency characteristic without using an isolator and also achieves low power consumption. The radio frequency power amplifier includes: a power amplifier which amplifies a radio frequency signal; a voltage supplying unit which supplies a collector voltage to the power amplifier; a current supplying unit which supplies a bias current to the power amplifier; and a bias current detecting unit which detects the bias current. The voltage supplying unit has a control unit which sets the power supply voltage at: a first voltage when the detected bias current is lower than a bias-current reference value; and a second voltage lower than the first voltage when the detected bias current is higher than the bias-current reference value.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: An output level of a transmission apparatus 1 is determined, depending on an attenuation amount of an attenuator 30, a gain of one of a high output level amplification section 17 and a low output level amplification section 18, which is used. A reference voltage Vref(H) is discontinuously changed. Depending on the magnitude of the reference voltage Vref(H), it is determined which of the amplification sections 17, 18 is used, and the attenuation amount of the attenuator 30 and the gain of the amplification section 17, 18 are also determined. When the magnitude of the reference voltage Vref(H) is changed, a sum of the attenuation amount of the attenuator 30 and a gain change amount of a switch amplification section 19 is substantially zero.

Abstract: A gain control circuit 12 comprises an FET 41 operating as a variable resistor. A gate terminal of the FET 41 is supplied with a control voltage VC applied to a gain control terminal 23. A source terminal and a drain terminal of the FET 41 are supplied with a reference voltage Vref1 obtained by a reference voltage circuit 13. The reference voltage Vref1 is controlled so as to compensate for a variation in the threshold voltage of the FET 41. The resistance value of the FET 41 is changed in accordance with the control voltage VC, and thus the gain of the high frequency amplification circuit 10 is also continuously changed.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: An output level of a transmission apparatus 1 is determined, depending on an attenuation amount of an attenuator 30, a gain of one of a high output level amplification section 17 and a low output level amplification section 18, which is used. A reference voltage Vref(H) is discontinuously changed. Depending on the magnitude of the reference voltage Vref(H), it is determined which of the amplification sections 17, 18 is used, and the attenuation amount of the attenuator 30 and the gain of the amplification section 17, 18 are also determined. When the magnitude of the reference voltage Vref(H) is changed, a sum of the attenuation amount of the attenuator 30 and a gain change amount of a switch amplification section 19 is substantially zero.

Abstract: A gain control circuit 12 comprises an FET 41 operating as a variable resistor. A gate terminal of the FET 41 is supplied with a control voltage VC applied to a gain control terminal 23. A source terminal and a drain terminal of the FET 41 are supplied with a reference voltage Vref1 obtained by a reference voltage circuit 13. The reference voltage Vref1 is controlled so as to compensate for a variation in the threshold voltage of the FET 41. The resistance value of the FET 41 is changed in accordance with the control voltage VC, and thus the gain of the high frequency amplification circuit 10 is also continuously changed.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A high-frequency circuit is provided that can prevent the generation of an undesired peak and contribute to the reduction in area of a chip. The high-frequency circuit includes an amplifying block 10 in which an amplifying element 11, a choke inductor 12, and a by-pass capacitor 13 are provided, and an amplifying block 20 in which an amplifying element 21, a choke inductor 22, and a by-pass capacitor 23 are provided. Electric power is supplied from a common power terminal 31 to the amplifying element 21 via the choke inductor 22 and to the amplifying element 11 via the choke inductor 12 and a resistive element 37. The amplifying elements 11 and 21, the choke inductors 12 and 22, the by-pass capacitors 13 and 23, and the resistive element 37 are formed on the same substrate.

Abstract: A high-frequency circuit is provided that can prevent the generation of an undesired peak and contribute to the reduction in area of a chip. The high-frequency circuit includes an amplifying block 10 in which an amplifying element 11, a choke inductor 12, and a by-pass capacitor 13 are provided, and an amplifying block 20 in which an amplifying element 21, a choke inductor 22, and a by-pass capacitor 23 are provided. Electric power is supplied from a common power terminal 31 to the amplifying element 21 via the choke inductor 22 and to the amplifying element 11 via the choke inductor 12 and a resistive element 37. The amplifying elements 11 and 21, the choke inductors 12 and 22, the by-pass capacitors 13 and 23, and the resistive element 37 are formed on the same substrate.