Patents by Inventor Tsunehisa Sakoda
Tsunehisa Sakoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7927941Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.Type: GrantFiled: June 17, 2010Date of Patent: April 19, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hiroshi Nomura, Takashi Saiki, Tsunehisa Sakoda
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Patent number: 7893508Abstract: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.Type: GrantFiled: September 11, 2006Date of Patent: February 22, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tsunehisa Sakoda, Kazuto Ikeda
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Publication number: 20100255668Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroshi NOMURA, Takashi Saiki, Tsunehisa Sakoda
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Patent number: 7768039Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.Type: GrantFiled: September 28, 2005Date of Patent: August 3, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hiroshi Nomura, Takashi Saiki, Tsunehisa Sakoda
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Patent number: 7521325Abstract: A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.Type: GrantFiled: July 28, 2005Date of Patent: April 21, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tsunehisa Sakoda, Masaomi Yamaguchi, Hiroshi Minakata, Yoshihiro Sugita, Kazuto Ikeda
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Publication number: 20070232004Abstract: A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.Type: ApplicationFiled: September 11, 2006Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: Tsunehisa Sakoda, Kazuto Ikeda
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Patent number: 7265401Abstract: A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.Type: GrantFiled: June 9, 2005Date of Patent: September 4, 2007Assignee: Fujitsu LimitedInventors: Masaomi Yamaguchi, Hiroshi Minakata, Tsunehisa Sakoda, Kazuto Ikeda
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Publication number: 20060292782Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.Type: ApplicationFiled: September 28, 2005Publication date: December 28, 2006Applicant: FUJITSU LIMITEDInventors: Hiroshi Nomura, Takashi Saiki, Tsunehisa Sakoda
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Publication number: 20060214243Abstract: A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.Type: ApplicationFiled: July 28, 2005Publication date: September 28, 2006Applicant: FUJITSU LIMITEDInventors: Tsunehisa Sakoda, Masaomi Yamaguchi, Hiroshi Minakata, Yoshihiro Sugita, Kazuto Ikeda
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Publication number: 20060172498Abstract: A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.Type: ApplicationFiled: June 9, 2005Publication date: August 3, 2006Applicant: FUJITSU LIMITEDInventors: Masaomi Yamaguchi, Hiroshi Minakata, Tsunehisa Sakoda, Kazuto Ikeda
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Publication number: 20050142715Abstract: A semiconductor device has: a silicon substrate; a silicon oxide layer formed on the surface of the silicon substrate; a high dielectric constant insulating film including a first oxide layer formed above the silicon oxide layer and made of a high dielectric constant film having a dielectric constant higher than silicon oxide and a first nitride layer formed above the first oxide layer and made of nitride having an oxygen intercepting capability, or a high dielectric constant insulating film including a first oxide film formed on the silicon oxide layer, a second oxide layer formed on the first oxide layer and a third oxide layer formed on the second oxide layer, the first and third oxide layers having an oxygen diffusion coefficient smaller than the second oxide layer; and a gate electrode formed on the high dielectric constant insulating layer and made of oxidizable material.Type: ApplicationFiled: October 27, 2004Publication date: June 30, 2005Applicant: FUJITSU LIMITEDInventors: Tsunehisa Sakoda, Yoshihiro Sugiyama, Masaomi Yamaguchi, Hiroshi Minakata