Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.

Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.

Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.

Abstract: A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection.

Abstract: A clock synchronization circuit receives a base clock, a first synchronization signal for synchronizing the base clock and a system clock, and a selection signal containing information about the division ratio of the system clock, holds the first synchronization signal over a predetermined time on the basis of the selection signal, and outputs, in synchronization with the base clock, a second synchronization signal for synchronizing the base clock and the system clock.

Abstract: When a processor has transitioned to an operation stop state, it is possible to reduce the power consumption of a cache memory while maintaining the consistency of cache data. A multiprocessor system includes first and second processors, a shared memory, first and second cache memories, a consistency management circuit for managing consistency of data stored in the first and second cache memories, a request signal line for transmitting a request signal for a data update request from the consistency management circuit to the first and second cache memories, an information signal line for transmitting an information signal for informing completion of the data update from the first and second cache memories to the consistency management circuit, and a cache power control circuit for controlling supply of a clock signal and power to the first and second cache memories in accordance with the request signal and the information signal.

Abstract: A clock signal generation circuit into which a first clock signal and a control signal based on an address are inputted, and a second clock signal based on said first clock signal is generated after a lapse of predetermined time from said input of the control signal.

Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.

Abstract: A semiconductor integrated circuit includes: a first circuit; and a second circuit configured to control supply of a first power to the first circuit. The first circuit includes: a third circuit comprising a group of flip-flops, whose internal state is erased in response to stop of the supply of the first power; and a fourth circuit in which an internal state of the fourth circuit is saved in retention flip-flops before the supply of the first power is stopped and recovered from the retention flip-flops in response to restart of the supply of the first power.

Abstract: A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: A clock signal generation circuit into which a first clock signal and a control signal based on an address are inputted, and a second clock signal based on said first clock signal is generated after a lapse of predetermined time from said input of the control signal.

Abstract: Disclosed is a digital circuit which comprises input signals A[n?1:0], SH[log2n?1:0], and DAT[n?1:0], a barrel shifter for outputting data B[n?1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation stage for dividing each of the digits of the input signals A and B into groups of m bits, and computing Gs, Ps, and addition results SUM0 when carry inputs are high and addition results SUM1 when the carry inputs are low, a carry computation circuit for computing a carry for each of the groups, and a SUM selection stage for selecting a SUM0 or a SUM1 computed for each of the groups according to each carry output by the carry computation circuit.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: Disclosed is a digital circuit which comprises input signals A[n?1:0], SH[log2n?1:0], and DAT[n?1:0], a barrel shifter for outputting data B[n?1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation stage for dividing each of the digits of the input signals A and B into groups of m bits, and computing Gs, Ps, and addition results SUM0 when carry inputs are high and addition results SUM1 when the carry inputs are low, a carry computation circuit for computing a carry for each of the groups, and a SUM selection stage for selecting a SUM0 or a SUM1 computed for each of the groups according to each carry output by the carry computation circuit.

Abstract: A Huffman-code decoder includes a coded data storage section, a code length detector for detecting the code length of an input Huffman code, an address calculator for calculating the address for the coded data for the input Huffman code, a value data storage section for storing a value data obtained by subtracting from the minimum code the address thereof, and a subtracter for subtracting the value data from the input Huffman code. Each of the value data storage section, subtracter and code length detector has a maximum of eight bits for the Huffman codes having a single to sixteen bits.