Patents by Inventor Tsunenobu Kouda

Tsunenobu Kouda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6359234
    Abstract: A package substrate in which a semiconductor chip is placed is disclosed. A through hole land (opposed conductor) connected to a signal wiring is opposite to a fixed electrical potential conductor through an insulator layer. The through hole land is disposed in a wiring layer on the outermost side of wiring layers of the package substrate. The through hole land connected to the signal wiring for input/output of signals at a higher frequency has a larger size. The through hole lands connected to the signal wiring for input/output of signals at a certain frequency and the through hole lands connected to the signal wiring for input/output of signals at a lower frequency than the certain frequency are alternately arranged. The through hole land, the insulator layer and the fixed electrical potential conductor form a capacitor and serve as a stub, thereby reducing impedance of the signal wiring connected thereto.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: March 19, 2002
    Assignee: NEC Corporation
    Inventor: Tsunenobu Kouda
  • Patent number: 5818105
    Abstract: A plastic covered semiconductor device that enables to simplify the structure and fabrication to reduce the assembly cost of the device and to reduce the thickness or height of the device. This device contains a substrate having a first surface and a second surface opposite to the first surface, a semiconductor chip mounted on or over the first surface, lead fingers joined to the first surface, interconnecting conductors electrically interconnecting the semiconductor chip with the corresponding lead fingers, respectively, and a plastic covering material formed to cover the first surface. Each lead finger is made of an inner part bonded to the first surface of the substrate and an outer part protruding the covering material. The covering material confines the semiconductor chip, the interconnecting conductors and the inner parts of the lead fingers. The second surface of the substrate is exposed from the covering material.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: October 6, 1998
    Assignee: NEC Corporation
    Inventor: Tsunenobu Kouda
  • Patent number: 5801438
    Abstract: In a multi-chip module, a laminate wiring board is formed with stepped recesses. Electrodes to be connected to the electrodes of a bare-chip semiconductor device are subjected to non-electrolytic gold plating. This realizes wire bonding which is as short in distance and as low in loop as possible. To seal each recess with insulating resin, use is made of screen printing using a mesh screen which has a great aperture ratio and a small thickness.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: September 1, 1998
    Assignee: NEC Corporation
    Inventors: Hirotsugu Shirakawa, Yasunori Tanaka, Tsunenobu Kouda