Abstract: A memory access method in a microcomputer for a CPU to fetch an instruction code from a memory when an instruction queue buffer does not contain the instruction code, comprising the steps of fetching the instruction code from a high-speed memory directly to the CPU, if the instruction code is in the high speed memory, or fetching the instruction code from a low-speed memory to the instruction queue buffer, if the instruction code is in the low-speed memory, then fetching the instruction code from the instruction queue buffer to the CPU.

Abstract: A microprogram control device controls a data path section provided in a CPU, which uses a microcode stored in a microprogram memory by using a microprogramming method. The control device includes an instruction register for storing an instruction code which is received from a data bus and an address generator for generating an address signal to access the microprogram memory, from the output of the instruction register. The address generator uses a first address decoder for decoding the type of the instruction from a particular bit in the instruction code and a second address decoder for decoding the addressing mode of the instruction from another particular bit of the instruction code. A third address decoder is included for designating the timing for accessing the microprogram memory at each cycle of the instruction.

Abstract: For obtaining a central processing unit to perform, with the same operation code, an operation in which a carry input is effective and an operation in which the carry input is invalid or an operation in which a borrow input is effective and an operation in which the borrow input is invalid, between an output of a carry and borrow flag and a carry and borrow input of an ALU there is provided a switching circuit to switch the input of the ALU by a control signal different from a control signal of the central processing unit due to an operation code.

Abstract: A microcomputer that reduces through current of output buffers, and thus, reduces power line fluctuation that occurs when a large number of the bus lines connected to output buffers change state at the same time. The through current (or punch-through current) is reduced through the use of a detector circuit that detects the number of bus lines which are changing state and a decoder circuit that changes the impedance of output buffers, which drive the bus lines to external components, when the number of bus lines changing state at a given time exceeds a predetermined number.

Abstract: An AND type read-only memory (D-A-ROM), includes a memory unit divided into blocks in a row direction and into sub-blocks a column direction, a Y decoder, an X decoder and a column selector. An output of the Y decoder and an output of the X decoder are connected to the memory blocks by first and second gate electrode connectors, respectively. A read control signal from the CPU is connected to each of the memory blocks by third gate electrode connectors. In addition, the output of the X decoder is supplied in parallel to each of the memory sub-blocks through bypass connectors including aluminum interconnections of a separately formed second layer. The read control signal is supplied in parallel to each of the memory sub-blocks through bypass interconnections of the second layer.

Abstract: A complementary IC device comprises: an n-semiconductor substrate; a p-well formed within the n-substrate: a n-channel FET (field effect transistor) formed on the p-well, the n-channel FET including an n-source connected to a first grounded line and an n-drain connected to an output line; a p-channel FET formed on the n-substrate, the p-channel FET including a p-source connected to a first voltage source line and a p-drain connected to the output line; a contact p-region formed on the p-well for providing electrical connection between the p-well and a second grounded line; and a contact n-region formed on the n-substrate for providing electrical connection between the n-substrate and a second voltage source line.

Abstract: A novel method for making complementary semiconductor IC devices is described. The method includes the steps of: preparing a N-type semiconductor substrate; preparing a first mask for forming a P-well in the N-type substrate; forming the P-well in the N-type substrate using the first mask; preparing a second mask for forming a first P-type diffusion regions in the substrate and in the P-well; preparing a third mask for forming N-type diffusion regions in the substrate and in the P-well; preparing a fourth mask for forming a second P-type diffusion regions in the unoccupied areas of the N-type substrate and the P-well by carrying out reversing, AND and OR processing of the first, second and third masks, and forming the P-type diffusion regions in the prescribed areas of the substrate and the P-well by placing the fourth mask on the substrate.

Abstract: A semiconductor memory includes a plurality of column selector circuits for storing data of a row memory cells specified by a row address decoder within a memory cell array and a plurality of column address decoders corresponding to the column selector circuits. The data of the row of memory cells selected by the row address decoder are stored in a plurality of column selector circuits, different address signals from the respective column address decoders are fed to the respective column selector circuits to simultaneously write or read the data in the different memory cells.

Abstract: A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.

Abstract: A complementary semiconductor integrated circuit for absorbing a noise comprises an n-type semiconductor substrate maintained at a supply voltage, a p-type well maintained at the reference voltage potential, an n-type region formed in the n-type semiconductor substrate and connected to the supply voltage, a polysilicon layer formed on the n-type region through an insulating film and connected to the reference voltage, whereby a capacitance is formed by the n-type region and the polysilicon layer formed on the n-type region through the insulating film. A noise included in the supply voltage is absorbed by the capacitance.

Abstract: A semiconductor read-only memory device includes first and second MOS field effect mode transistors (MOSFET) as memory elements storing either one of binary values of binary information. The first MOSFET has such a relatively long effective gate length that it becomes conductive upon receipt of a first relatively high gate voltage applied thereto as a memory selection signal and becomes non-conductive upon receipt of a second relatively low gate voltage. The second MOSFET, on the other hand, has such a relatively short effective gate length that it becomes conductive whether the first or second gate voltage is applied thereto.