Patents by Inventor Tsunenori Yamauchi

Tsunenori Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7348630
    Abstract: The semiconductor device has a semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate at both sides of each of the gate electrodes. The semiconductor device also has drift layers formed in the surface layer of the semiconductor substrate between the gate electrodes and one of the impurity diffusion layers as a same conduction type as the impurity diffusion layers. The gate electrodes are made of metal including aluminum, and each is formed in an overhang shape. The semiconductor device can provide an LDMOS transistor enhanced in maximum transmission frequency and power gain and capable of a high-frequency operation with high efficiency as a basic element of a high-frequency power amplifier.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: March 25, 2008
    Assignee: Fujitsu Limited
    Inventors: Tsunenori Yamauchi, Shunji Nakamura
  • Publication number: 20050179085
    Abstract: Substitution reaction between polysilicon and Al (aluminum) is utilized. Namely, polysilicon films are formed by patterning at first as in the related art, and after an Al film is formed on an interlayer insulating film to be in contact with the polysilicon films, the polysilicon films in the interlayer insulating film 9 are replaced with Al by heat treatment. By patterning, gate electrodes constituted of Al low in gate parasite resistance and high in mobility is formed.
    Type: Application
    Filed: July 29, 2004
    Publication date: August 18, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Tsunenori Yamauchi, Shunji Nakamura
  • Patent number: 6838349
    Abstract: The semiconductor device comprises a first semiconductor layer 14 formed on a semiconductor substrate 10; an outgoing base electrode 26 formed on the first semiconductor layer 14; a base layer 32 formed on the first semiconductor layer, connected to the outgoing base electrode at a side surface of the outgoing base electrode, and formed of silicon germanium containing carbon; and a second semiconductor layer 36 formed on the base layer. The base layer 32 of silicon germanium contains carbon, which prevents the action of interstitial silicon atoms, which are very influential to diffusion of boron. As a result, when the emitter layer 36, etc. are subjected to heat processing at, e.g., about 950° C., the diffusion of boron out of the base layer 32 can be prevented.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: January 4, 2005
    Assignee: Fujitsu Limited
    Inventor: Tsunenori Yamauchi
  • Patent number: 6528382
    Abstract: A semiconductor device comprises a silicon substrate 10 of a resistivity above or equal to 800 &OHgr;·cm and an oxygen concentration under or equal to 5×1017 cm−3, and an inductor 32b formed in the silicon substrate. A concentration of oxygen contained in the silicon substrate is set to be low, whereby the silicon substrate is less vulnerable to thermal donor effect, and even in a case that a silicon substrate of high resistivity is used, a semiconductor device which suppresses conversion of a conduction type of the silicon substrate while having an inductance of high Q. It is not necessary to bury a highly resistive layer in the silicon substrate, whereby a semiconductor device having an inductance of high Q can be fabricated by simple fabrication steps, which contributes to cost reduction of the semiconductor device.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Tsunenori Yamauchi, Hiroshi Kaneta, Katsuhiro Homma
  • Publication number: 20030025114
    Abstract: The semiconductor device comprises a first semiconductor layer 14 formed on a semiconductor substrate 10; an outgoing base electrode 26 formed on the first semiconductor layer 14; a base layer 32 formed on the first semiconductor layer, connected to the outgoing base electrode at a side surface of the outgoing base electrode, and formed of silicon germanium containing carbon; and a second semiconductor layer 36 formed on the base layer. The base layer 32 of silicon germanium contains carbon, which prevents the action of interstitial silicon atoms, which are very influential to diffusion of boron. As a result, when the emitter layer 36, etc. are subjected to heat processing at, e.g., about 950° C., the diffusion of boron out of the base layer 32 can be prevented.
    Type: Application
    Filed: January 24, 2002
    Publication date: February 6, 2003
    Applicant: Fujitsu Limited
    Inventor: Tsunenori Yamauchi
  • Publication number: 20020064923
    Abstract: A semiconductor device comprises a silicon substrate 10 of a resistivity above or equal to 800 &OHgr;·cm and an oxygen concentration under or equal to 5×1017 cm−3, and an inductor 32b formed in the silicon substrate. A concentration of oxygen contained in the silicon substrate is set to be low, whereby the silicon substrate is less vulnerable to thermal donor effect, and even in a case that a silicon substrate of high resistivity is used, a semiconductor device which suppresses conversion of a conduction type of the silicon substrate while having an inductance of high Q. It is not necessary to bury a highly resistive layer in the silicon substrate, whereby a semiconductor device having an inductance of high Q can be fabricated by simple fabrication steps, which contributes to cost reduction of the semiconductor device.
    Type: Application
    Filed: June 19, 2001
    Publication date: May 30, 2002
    Applicant: Fujitsu Limited
    Inventors: Tsunenori Yamauchi, Hiroshi Kaneta, Katsuhiro Homma
  • Patent number: 5518937
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: May 21, 1996
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5270224
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: December 14, 1993
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi
  • Patent number: 5111266
    Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: May 5, 1992
    Assignee: Fujitsu Limited
    Inventors: Yuji Furumura, Fumitake Mieno, Tsutomu Nakazawa, Takashi Eshita, Mamoru Maeda, Tsunenori Yamauchi