Abstract: A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer system and the second microcomputer system.

Abstract: When a CPU outputs an address for read-out from a memory, access to a cache memory is immediately started by use of its address signal, and in the mean time a cache controller determines whether or not the data required by the CPU exists in the cache memory and, if so, generates a selection signal for outputting only the data read out from a desired bank of the cache memory to a data bus. Acccordingly, the time necessary for address comparison in the cache controller is not added to the access cycle time of the cache memory so that the overall access time can be shortened and the through-put of the system can be improved.

Abstract: A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer system and the second microcomputer system.

Abstract: When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle.

Abstract: In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.

Abstract: A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control.

Abstract: In an apparatus for decoding cyclic codes generated by a generator polynomial ##EQU1## (where P.sub.i (x) is a m.sub.i -order irreducible polynomial) including 0-th to l-th feedback shift registers corresponding to the terms (x.sup.c +1) and P.sub.i (x), a coincidence circuit for detecting coincidence of a predetermined number of low order bits of said 0-th to l-th feedback shift registers and all-zero conditions of a high order bits, the predetermined number being a minimum one of numbers of bits (c, m.sub.1, m.sub.2, . . . m.sub.

Abstract: A data buffer is connected to the first and second processor and the first processor sends a start signal to the second processor, which responds to the start signal by reading data from a data source, such as an input/output device, and then writes the read out data into the data buffer. After conclusion of the writing operation, the second processor sends an end signal to the first processor which is admitted to start sending data stored in the buffer to a host processor after receipt of the start signal. The start signal and the end signal are provided to the second processor and the first processor respectively, after passing through a synchronizing circuit.

Abstract: In a multiple stage data transfer circuit, suitable for transferring a plurality of bits to or from a bit processor or 1-bit arithmetic logic unit, each bit stage includes a shift register portion and a latch portion. Each shift register(S/R) portion is constructed of a series circuit consisting of a static (input) inverter, a switching element, and a dynamic (output) inverter. Each latch portion is constructed of a closed loop consisting of a static inverter, a switching element, and a dynamic inverter. Each bit stage also includes a data transfer switch element, which may be activated through an externally connected control line. The data transfer switch is coupled beween the data output terminal of the S/R switch and the data output terminal of the latch switch. The S/R and latch portion switches are activated by two different clocks, with a phase deviation therebetween of one-half cycle. When the S/R switch and data transfer switch are both "ON", data may flow from the S/R's input inverter to the latch.

Abstract: In a pulse frequency multiplying circuit, a first capacitor charged to a given potential is discharged through a first constant-current circuit during a period corresponding to a pulse width of a reference pulse. Then, the terminal voltage of the first capacitor is applied as a reference voltage to one input terminal of a comparator circuit. A triangle wave voltage formed by alternately discharging a pair of second capacitors charged to a given potential, through a second constant-current circuit with a current value n times that in the first constant-current circuit, is applied to the other input terminal of the comparator circuit. The output from the comparator circuit operates a flip-flop circuit. In accordance with the output signal, the charge/discharge operation of said second capacitors is switched, whereby said flip-flop circuit produces a pulse with a frequency n times that of the reference pulse.

Abstract: A signal converter includes a generator for generating first and second clock signals having recurrence periods equal to each other and phases different from each other, an input for receiving as a signal to be converted a signal which has signal levels not lower than a predetermined level during an arbitrary period of time, a counter for counting the first clock signals from the generator in a period of time corresponding to the signal period of time, and an output arrangement. The output arrangement provides for delivering either of two signals in dependence on which of time intervals determined by the first and second clock signals an end of said signal period of time lies in, whereby signals of the counter and the output arrangement are used as a converted signal.