Patents by Inventor Tsuneo Funatsu

Tsuneo Funatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor storage device using redundancy method
    Patent number: 6421285
    Abstract: A semiconductor storage device includes a redundancy circuit, which replaces a defective memory cell with a redundancy memory cell. The semiconductor storage device further includes a charge pump used for programming redundancy information by performing dielectric breakdown selectively to a capacity. In addition, a redundancy control circuit included in the semiconductor storage device supplies a fixed charge to the capacity, and refreshes the capacity, thereby reproducing the redundancy information programmed by use of the charge pump. Additionally, the redundancy control unit supplies the redundancy information to a redundancy circuit.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: July 16, 2002
    Assignee: Fujitsu Limited
    Inventors: Yasurou Matsuzaki, Tsuneo Funatsu
  • Semiconductor storage device using redundancy method
    Publication number: 20020018363
    Abstract: A semiconductor storage device includes a redundancy circuit, which replaces a defective memory cell with a redundancy memory cell. The semiconductor storage device further includes a charge pump used for programming redundancy information by performing dielectric breakdown selectively to a capacity. In addition, a redundancy control circuit included in the semiconductor storage device supplies a fixed charge to the capacity, and refreshes the capacity, thereby reproducing the redundancy information programmed by use of the charge pump. Additionally, the redundancy control unit supplies the redundancy information to a redundancy circuit.
    Type: Application
    Filed: May 16, 2001
    Publication date: February 14, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Yasurou Matsuzaki, Tsuneo Funatsu
  • Semiconductor device and a method of manufacturing the same
    Patent number: 4497106
    Abstract: A semiconductor device comprising at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, has an electrode for each region of the bipolar transistor and the MIS FET. Each electrode has the same conductivity type as the corresponding region and is connected to ohmic contact with the surface of the corresponding region.
    Type: Grant
    Filed: October 28, 1981
    Date of Patent: February 5, 1985
    Assignee: Fujitsu Limited
    Inventors: Yoshinobu Momma, Tsuneo Funatsu, Atusi Sasaki
  • Method of producing an IIL semiconductor device utilizing self-aligned thickened oxide patterns
    Patent number: 4420874
    Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.
    Type: Grant
    Filed: January 18, 1982
    Date of Patent: December 20, 1983
    Assignee: Fujitsu Limited
    Inventor: Tsuneo Funatsu
  • Semiconductor device and a method of producing the same
    Patent number: 4375645
    Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.
    Type: Grant
    Filed: December 19, 1979
    Date of Patent: March 1, 1983
    Assignee: Fujitsu Limited
    Inventor: Tsuneo Funatsu