Patents by Inventor Tsuneo Hamaguchi

Tsuneo Hamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259711
    Abstract: An electromagnetic wave absorption sheet is arranged to contact an upper surface and side surfaces of an electronic component mounted on a wiring board, a heat conduction plate is arranged to contact the electromagnetic wave absorption sheet, a heat transfer sheet is arranged to contact the heat conduction plate, and a heat dissipation member is arranged to contact the heat transfer sheet. Heat conductive particles contained in the heat transfer sheet contact a flat surface portion of the heat conduction plate. The electromagnetic wave absorption sheet, the heat conduction plate, and the heat transfer sheet are interposed between the heat dissipation member and the electronic component, as a heat conduction member for conducting heat generated in the electronic component and the like to the heat dissipation member.
    Type: Application
    Filed: November 2, 2017
    Publication date: August 22, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsuneo HAMAGUCHI, Tomohiro TANISHITA, Shota SATO
  • Publication number: 20180343736
    Abstract: A printed board includes an insulating layer, and radiation vias penetrating printed board are formed in both a first region overlapping electronic component and a second region outside the first region. A plurality of conductor layers included in printed board are cross-connected to a plurality of radiation vias. Diffusion radiator includes a thermal diffusion plate, a radiation member, and a cooling body. Radiation member is in close contact with one of main surfaces of cooling body, and thermal diffusion plate is in close contact with one of main surfaces of radiation member on the opposite side to cooling body. One of main surfaces of thermal diffusion plate on the opposite side to radiation member is bonded to a conductor layer on the other main surface of printed board so as to close the plurality of radiation vias.
    Type: Application
    Filed: November 28, 2016
    Publication date: November 29, 2018
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shota SATO, Tsuneo HAMAGUCHI, Yuji SHIRAKATA, Kenta FUJII
  • Patent number: 9484479
    Abstract: A solar cell module in the present invention includes: a wiring member electrically connecting solar cell elements to each other; and a structure in which a solder bonding portion is formed by bonding a collecting electrode, which is provided on a light receiving surface of the solar cell element, extends in a first direction parallel to the wiring member, and has a width smaller than that of the wiring member in a cross section vertical to the first direction, and the wiring member together by melting solder, a cross-sectional shape of the solder bonding portion vertical to the first direction has a shape that gradually narrows toward the collecting electrode from a lower surface of the wiring member, and a side surface of the solder bonding portion and a side surface of the wiring member are covered with a thermosetting resin.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 1, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Yoshimi Yabugaki, Daisuke Echizenya, Jun Fujita, Tomoo Takayama, Shinsuke Miyamoto
  • Patent number: 9324895
    Abstract: A plurality of thin linear thin wire electrodes are formed entirely over a first surface that is a light receiving surface of a solar cell element, a back surface collecting electrode is formed on a second surface that is a back surface of the solar cell element, and a wiring member which draws power is connected to each of the thin wire electrode and the back surface collecting electrode. The thin wire electrode and the wiring member are bonded with solder and side surfaces of the solder bonding portion in a longitudinal direction along the wiring member are coated with a thermosetting resin, and, in a region excluding the thin wire electrodes, the wiring member and the first surface are bonded with a thermosetting resin. The wiring member and the thin wire electrodes are bonded to have a sufficient mechanical bonding strength and high bonding reliability.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 26, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Yoshimi Yabugaki, Daisuke Echizenya, Shinsuke Miyamoto
  • Publication number: 20140251409
    Abstract: A solar cell module in the present invention includes: a wiring member electrically connecting solar cell elements to each other; and a structure in which a solder bonding portion is formed by bonding a collecting electrode, which is provided on a light receiving surface of the solar cell element, extends in a first direction parallel to the wiring member, and has a width smaller than that of the wiring member in a cross section vertical to the first direction, and the wiring member together by melting solder, a cross-sectional shape of the solder bonding portion vertical to the first direction has a shape that gradually narrows toward the collecting electrode from a lower surface of the wiring member, and a side surface of the solder bonding portion and a side surface of the wiring member are covered with a thermosetting resin.
    Type: Application
    Filed: October 17, 2012
    Publication date: September 11, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tsuneo Hamaguchi, Yoshimi Yabugaki, Daisuke Echizenya, Jun Fujita, Tomoo Takayama, Shinsuke Miyamoto
  • Publication number: 20130312810
    Abstract: In a solar battery module including a plurality of solar battery elements each including electrodes that are electrically connected by an electrically conductive wiring member, the electrode and the wiring member are welded by solder on the electrode, resin is arranged while covering at least a side surface of a solder-bonded portion between the solder and the electrode, and a wetted height of the resin on a side surface of the wiring member is lower than the top of wiring member, so that welding by the solder can be reinforced and the bonding reliability can be improved.
    Type: Application
    Filed: April 5, 2012
    Publication date: November 28, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Yoshimi Yabugaki, Shinsuke Miyamoto, Yasumichi Hatanaka
  • Publication number: 20130233375
    Abstract: A plurality of thin linear thin wire electrodes are formed entirely over a first surface that is a light receiving surface of a solar cell element, a back surface collecting electrode is formed on a second surface that is a back surface of the solar cell element, and a wiring member which draws power is connected to each of the thin wire electrode and the back surface collecting electrode. The thin wire electrode and the wiring member are bonded with solder and side surfaces of the solder bonding portion in a longitudinal direction along the wiring member are coated with a thermosetting resin, and, in a region excluding the thin wire electrodes, the wiring member and the first surface are bonded with a thermosetting resin. The wiring member and the thin wire electrodes are bonded to have a sufficient mechanical bonding strength and high bonding reliability.
    Type: Application
    Filed: June 20, 2011
    Publication date: September 12, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Yoshimi Yabugaki, Daisuke Echizenya, Shinsuke Miyamoto
  • Publication number: 20120091572
    Abstract: The semiconductor package includes a package wiring board having an element housing recessed portion on its top surface to house a semiconductor element; multiple side electrodes which are arranged on the outer side surface of the package wiring board and soldered to multiple motherboard electrodes arranged on a motherboard; a semiconductor element fixed onto the bottom surface of the element housing recessed portion; and an element electrode arranged on the bottom of the element housing recessed portion and electrically connected to the semiconductor element and the side electrodes. The package wiring board has a multilayered structure in which woven fabric and a resin adhesive layer are alternately laminated, and the resin adhesive layer is formed of a resin adhesive that contains inorganic filler particles.
    Type: Application
    Filed: June 22, 2009
    Publication date: April 19, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Hamaguchi, Ikio Sugiura, Hiroo Sakamoto, Masaki Iwata, Takashi Shirase, Takashi Okamuro
  • Publication number: 20110007762
    Abstract: To constitute an optical module in which a comb-shaped submount is fixed on a heat sink and a device having an optical functioning unit is mounted on the comb-shaped submount, a stress buffering block that relaxes a thermal stress acting between the heat sink and the comb-shaped submount is placed between the heat sink and the comb-shaped submount. With this configuration, a thermal stress acting between the comb-shaped submount and the device mounted thereon is relaxed, and as a result, long-term reliability of bonding parts between the comb-shaped submount and the device is enhanced.
    Type: Application
    Filed: March 14, 2008
    Publication date: January 13, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Keiichi Fukuda, Motoaki Tamaya, Shinichi Oe, Tsuneo Hamaguchi, Akira Nakamura
  • Patent number: 6905911
    Abstract: A semiconductor device includes projecting electrodes formed on one surface of a wiring substrate so as to have a prescribed height, a semiconductor chip having a thickness smaller than the height of the projecting electrodes, and an electronic component having a thickness larger than that of the semiconductor chip and mounted on the other surface of the wiring substrate so that the wiring substrate is warped to be recessed at the one surface. Thus, the rigidity as well as the spacing between the semiconductor chip and the mounting board are assured. Moreover, the semiconductor device having a logic LSI mounted on both surfaces of a wiring substrate is mounted on a mounting board in a housing with projecting electrodes having a prescribed height interposed therebetween, wherein the wiring substrate is warped to be recessed on the side having the projecting electrodes.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: June 14, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsuneo Hamaguchi, Kenji Kagata
  • Publication number: 20040021212
    Abstract: A semiconductor device includes projecting electrodes formed on one surface of a wiring substrate so as to have a prescribed height, a semiconductor chip having a thickness smaller than the height of the projecting electrodes, and an electronic component having a thickness larger than that of the semiconductor chip and mounted on the other surface of the wiring substrate so that the wiring substrate is warped to be recessed at the one surface. Thus, the rigidity as well as the spacing between the semiconductor chip and the mounting board are assured. Moreover, the semiconductor device having a logic LSI mounted on both surfaces of a wiring substrate is mounted on a mounting board in a housing with projecting electrodes having a prescribed height interposed therebetween, wherein the wiring substrate is warped to be recessed on the side having the projecting electrodes.
    Type: Application
    Filed: July 8, 2003
    Publication date: February 5, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tsuneo Hamaguchi, Kenji Kagata
  • Patent number: 6633078
    Abstract: A semiconductor device includes projecting electrodes formed on one surface of a wiring substrate so as to have a prescribed height, a semiconductor chip having a thickness smaller than the height of the projecting electrodes, and an electronic component having a thickness larger than that of the semiconductor chip and mounted on the other surface of the wiring substrate so that the wiring substrate is warped to be recessed at the one surface. Thus, the rigidity as well as the spacing between the semiconductor chip and the mounting board are assured. Moreover, the semiconductor device having a logic LSI mounted on both surfaces of a wiring substrate is mounted on a mounting board in a housing with projecting electrodes having a prescribed height interposed therebetween, wherein the wiring substrate is warped to be recessed on the side having the projecting electrodes.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: October 14, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsuneo Hamaguchi, Kenji Kagata
  • Publication number: 20020158324
    Abstract: It is an object of the present invention to provide a low-cost semiconductor device including a semiconductor chip mounted on both surfaces of a wiring substrate without degrading electric characteristics, a method for manufacturing an electronic equipment, an electronic equipment, and a portable information terminal
    Type: Application
    Filed: November 20, 2001
    Publication date: October 31, 2002
    Inventors: Tsuneo Hamaguchi, Kenji Kagata
  • Patent number: 5821762
    Abstract: A high-speed, high-density, small-sized, low-cost semiconductor device wherein the feeder substrate 2 for supplying power to the semiconductor elements 3 as a bare chip has the containers 2a for containing the semiconductor elements 3, the semiconductor elements 3 are bonded to the wiring layer 1b of the signal transmission substrate 1 for transmitting signals to the semiconductor elements 3 and contained in the containers 2a, the containers 2a are covered with the signal transmission substrate 1, and the signal transmission substrate 1 is superposed upon and bonded to the feeder substrate 2.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: October 13, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsuneo Hamaguchi, Kenji Kagata, Goro Izuta, Mitsunori Ishizaki, Osamu Hayashi, Susumu Hoshinouchi
  • Patent number: 5290971
    Abstract: This invention relates to printed circuit boards and a method of fabricating same wherein the input/output terminals are integral with the wiring layer of the printed circuit board. This arrangement allows for a higher density of input/output connections than is possible with conventional printed circuit boards.
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: March 1, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsuneo Hamaguchi, Masanobu Kohara
  • Patent number: 5106197
    Abstract: A liquid crystal display apparatus which realizes a large-scale display by connecting a plurality of liquid crystal panels wherein on an electrode substrate having data bus lines and gate bus lines on one surface are formed extension lines each extending from an end of each of the data bus lines and gate bus lines to the opposite surface of the electrode substrate, and a plurality of the electrode substrates are mounted on a substrate on which electrodes are provided to electrically connect the extension lines of the data bus lines or gate bus lines on one electrode substrate with the corresponding ones on other electrode substrate.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: April 21, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirofumi Ohuchida, Tsuneo Hamaguchi
  • Patent number: 4870475
    Abstract: A method of manufacturing a semiconductor device, has the steps of forming an element on a semiconductor substrate, adhering an element formation surface of the semiconductor substrate to another substrate through an insulating adhesive layer, removing the semiconductor substrate till the element formation layer is exposed, forming an insulating film on the element formation layer, removing the insulating film at a portion where contact holes are to be formed to expose the element formation layer or till the underlying element formation layer is exposed to expose electrode wirings, and forming wiring patterns connected thereto. A bipolar transistor manufactured by this method is also disclosed.
    Type: Grant
    Filed: October 29, 1986
    Date of Patent: September 26, 1989
    Assignee: NEC Corporation
    Inventors: Nobuhiro Endo, Tsuneo Hamaguchi