Abstract: An improved method of testing and inspecting a plasma display panel. In a plasma display panel, a plurality of cells are formed at an intersection of each electrode disposed in a row direction and in a column direction of the panel. A field is formed of a plurality of sub-fields, and the combination of the sub-fields enables the panel to have a gradation display. In the inspection method, an address pulse voltage is not applied to a target cell to be inspected in a predetermined sub-field, but is applied to at least one cell of the cells adjacent to the target cell, and the address pulse voltage is applied to the target cell in the successive sub-field. If the barrier ribs of the target cell have an imperfection, wall charges of the cell are affected by the discharge occurred in an adjacent cell, and the target cell fails to light on in the successive sub-field. The inspection method can thus detect lighting failure caused by defective barrier ribs.

Abstract: A light inspection device for performing lighting inspection of a display panel contains a circuit board having a driving circuit for a lighting display panel; a conductive chassis that functions as the ground potential of the driving circuit; and a conductive support member fixed to the chassis for fixing the circuit board. The chassis and the support member are joined via soft metal.

Abstract: Disclosed is an improved method of performing lighting inspection on a plasma display panel. In a plasma display panel, a plurality of cells is formed at an intersection of each electrode disposed in a row direction and in a column direction of the panel. A field is formed of a plurality of sub-fields, and the combination of the sub-fields enables the panel to have gradation display. In the inspection method, address pulse voltage is not applied to a target cell to be inspected in a predetermined sub-field, but applied to at least one cell of the cells adjacent to the target cell, and the address pulse voltage is applied to the target cell in the successive sub-field. If the barrier ribs of the target cell have an imperfection, wall charges of the cell are affected by the discharge occurred in an adjacent cell, and the target cell fails to light on in the successive sub-field. The inspection method can thus detect lighting failure caused by defective barrier ribs.

Abstract: After forming, on a substrate, a first insulating film with a relatively low dielectric constant and low mechanical strength, the first insulating film is patterned. After forming, on the substrate, a second insulating film with a relatively high dielectric constant and high mechanical strength, the second insulating film is planarized by polishing, so as to form a thinned portion of the second insulating film on the patterned first insulating film. An interconnect groove is formed in the thinned portion of the second insulating film and the patterned first insulating film, and then, a buried interconnect is formed in the interconnect groove.

Abstract: After forming a first insulating film with a relatively low dielectric constant and low mechanical strength on a semiconductor substrate, a mask pattern is formed on a desired region of the first insulating film. Then, the first insulating film is patterned by conducting selective etching using the mask pattern. After forming a second insulating film with a relatively high dielectric constant and high mechanical strength on the semiconductor substrate, the second insulating film is planarized by polishing, so as to expose a face of the patterned first insulating film. An interconnect groove is formed in the patterned first insulating film, and a buried interconnect is formed in the interconnect groove.

Abstract: After forming, on a substrate, a first insulating film with a relatively low dielectric constant and low mechanical strength, the first insulating film is patterned. After forming, on the substrate, a second insulating film with a relatively high dielectric constant and high mechanical strength, the second insulating film is planarized by polishing, so as to form a thinned portion of the second insulating film on the patterned first insulating film. An interconnect groove is formed in the thinned portion of the second insulating film and the patterned first insulating film, and then, a buried interconnect is formed in the interconnect groove.

Abstract: After forming a first insulating film with a relatively low dielectric constant and low mechanical strength on a semiconductor substrate, a mask pattern is formed on a desired region of the first insulating film. Then, the first insulating film is patterned by conducting selective etching using the mask pattern. After forming a second insulating film with a relatively high dielectric constant and high mechanical strength on the semiconductor substrate, the second insulating film is planarized by polishing, so as to expose a face of the patterned first insulating film. An interconnect groove is formed in the patterned first insulating film, and a buried interconnect is formed in the interconnect groove.