Patents by Inventor Tsuneo Kawamata

Tsuneo Kawamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11564665
    Abstract: An object of the invention is to provide an ultrasonic probe, an ultrasonic diagnostic device, and a manufacturing method of the ultrasonic probe, which are capable of reducing a product defect rate. An ultrasonic probe according to one embodiment includes a plurality of channels. Each of the plurality of channels includes a vibrator that outputs an ultrasonic wave, and a transmission circuit unit that changes an output in response to an input transmission signal and causes the vibrator to output the ultrasonic wave by driving the vibrator with the output. Here, the transmission circuit unit includes a stop signal holding circuit that holds a stop signal when the stop signal is input in advance, and selects whether to change the output in response to the transmission signal based on whether the stop signal is held.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 31, 2023
    Assignee: FUJIFILM Healthcare Corporation
    Inventors: Toru Yazaki, Yutaka Igarashi, Yoshihiro Hayashi, Tsuneo Kawamata
  • Publication number: 20200300817
    Abstract: An object of the invention is to provide an ultrasonic probe, an ultrasonic diagnostic device, and a manufacturing method of the ultrasonic probe, which are capable of reducing a product defect rate. An ultrasonic probe according to one embodiment includes a plurality of channels. Each of the plurality of channels includes a vibrator that outputs an ultrasonic wave, and a transmission circuit unit that changes an output in response to an input transmission signal and causes the vibrator to output the ultrasonic wave by driving the vibrator with the output. Here, the transmission circuit unit includes a stop signal holding circuit that holds a stop signal when the stop signal is input in advance, and selects whether to change the output in response to the transmission signal based on whether the stop signal is held.
    Type: Application
    Filed: February 26, 2020
    Publication date: September 24, 2020
    Inventors: Toru Yazaki, Yutaka Igarashi, Yoshihiro Hayashi, Tsuneo Kawamata
  • Patent number: 8358172
    Abstract: A peaking circuit for adjusting peaking of a high-frequency signal, comprises: a first inductor; a second inductor which is electromagnetically coupled with the first inductor; a signal input section which receives an input signal; a transistor which adjusts electric current passing through the second inductor according to the input signal inputted via the signal input section; and a signal output section which outputs a signal whose peaking has been adjusted by the first inductor. Mutual inductance of the electromagnetically coupled first and second inductors is changed by the adjustment of the electric current passing through the second inductor, according to the input signal inputted via the signal input section, with the use of the transistor, thereby adjusting the peaking of signal waveform of electric current passing through the first inductor, and the signal subjected to the peaking adjustment is outputted from the signal output section.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 22, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Norio Chujo, Tsuneo Kawamata, Toshiaki Takai
  • Publication number: 20110241778
    Abstract: A peaking circuit for adjusting peaking of a high-frequency signal, comprises: a first inductor; a second inductor which is electromagnetically coupled with the first inductor; a signal input section which receives an input signal; a transistor which adjusts electric current passing through the second inductor according to the input signal inputted via the signal input section; and a signal output section which outputs a signal whose peaking has been adjusted by the first inductor. Mutual inductance of the electromagnetically coupled first and second inductors is changed by the adjustment of the electric current passing through the second inductor, according to the input signal inputted via the signal input section, with the use of the transistor, thereby adjusting the peaking of signal waveform of electric current passing through the first inductor, and the signal subjected to the peaking adjustment is outputted from the signal output section.
    Type: Application
    Filed: February 9, 2011
    Publication date: October 6, 2011
    Inventors: Norio CHUJO, Tsuneo Kawamata, Toshiaki Takai
  • Patent number: 7016214
    Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: March 21, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tsuneo Kawamata, Masatoshi Hasegawa, Keinosuke Toriyama, Tomofumi Hokari
  • Publication number: 20050077582
    Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.
    Type: Application
    Filed: October 5, 2004
    Publication date: April 14, 2005
    Inventors: Tsuneo Kawamata, Masatoshi Hasegawa, Keinosuke Toriyama, Tomofumi Hokari