Patents by Inventor Tsuneo Mishima

Tsuneo Mishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7002435
    Abstract: There is disclosed a variable capacitance circuit which comprises: first to Nth variable capacitance elements C1-CN (N is an odd number) sequentially connected in series between an input terminal I and an output terminal O, whose capacitances change depending on voltage applied thereto; an ith bias line on the input terminal side provided between an input terminal portion of the first variable capacitance element and a connection point between a 2ith variable capacitance element and a (2i+1)th variable capacitance element; and an ith bias line on the output terminal side provided between an output terminal portion of the Nth variable capacitance element and a connection point between a (2i?1)th variable capacitance element and the 2ith variable capacitance element, where N and i are integers satisfying N=2n+1, n?1, 1?i?n.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: February 21, 2006
    Assignee: Kyocera Corporation
    Inventors: Tsuneo Mishima, Tetsuya Kishino, Hideharu Kurioka
  • Patent number: 6806553
    Abstract: It is an object of the invention to provide a variable capacitor constituted such that, even when an external control voltage is applied, a stable dielectric constant of the dielectric layer can be obtained. A variable capacitor constituted such that a dielectric layer whose dielectric constant is changed by the application of an external voltage is held between an upper electrode layer and a lower electrode layer, wherein a plurality of capacitance-producing regions a, b are connected to each other.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: October 19, 2004
    Assignee: Kyocera Corporation
    Inventors: Yukihiko Yashima, Kazuhiro Kusabe, Tsuneo Mishima, Tetsuya Kishino
  • Publication number: 20040164819
    Abstract: There is disclosed a variable capacitance circuit which comprises: first to Nth variable capacitance elements C1-CN (N is an odd number) sequentially connected in series between an input terminal I and an output terminal O, whose capacitances change depending on voltage applied thereto; an ith bias line on the input terminal side provided between an input terminal portion of the first variable capacitance element and a connection point between a 2ith variable capacitance element and a (2i+1)th variable capacitance element; and an ith bias line on the output terminal side provided between an output terminal portion of the Nth variable capacitance element and a connection point between a (2i−1)th variable capacitance element and the 2ith variable capacitance element, where N and i are integers satisfying N=2n+1, n≧1, 1≦i≦n.
    Type: Application
    Filed: September 25, 2003
    Publication date: August 26, 2004
    Applicant: KYOCERA CORPORATION
    Inventors: Tsuneo Mishima, Tetsuya Kishino, Hideharu Kurioka
  • Publication number: 20030071300
    Abstract: It is an object of the invention to provide a variable capacitor constituted such that, even when an external control voltage is applied, a stable dielectric constant of the dielectric layer can be obtained. A variable capacitor constituted such that a dielectric layer whose dielectric constant is changed by the application of an external voltage is held between an upper electrode layer and a lower electrode layer, wherein a plurality of capacitance-producing regions a, b are connected to each other.
    Type: Application
    Filed: March 28, 2002
    Publication date: April 17, 2003
    Inventors: Yukihiko Yashima, Kazuhiro Kusabe, Tsuneo Mishima, Tetsuya Kishino
  • Patent number: 6266227
    Abstract: A thin-film capacitor in which a plurality of capacitor elements are arranged side by side, each capacitor element being constituted by a dielectric layer, a first electrode layer formed on the lower surface of said dielectric layer, and a second electrode layer formed on the upper surface of said dielectric layer, wherein among the neighboring capacitor elements, there are provided first terminal electrode layers for connecting the neighboring first electrode layers together, and second terminal electrode layers for connecting the neighboring second electrode layers together; said first terminal electrode layers and said second terminal electrode layers are so arranged as will not be overlapped one upon the other; and said first and second terminal electrode layers are provided with an external terminal, respectively. The capacitor can be easily mounted on an external board and has a low-inductance structure.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: July 24, 2001
    Assignee: Kyocera Corporation
    Inventors: Shigeo Konushi, Tsuneo Mishima